Registers in AddressMap abc_soc_top/dlnk/pcieabc78/DWC_pcie_dbi/DWC_PCIE_USP
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AddressMap abc_soc_top/dlnk/pcieabc78/DWC_pcie_dbi/DWC_PCIE_USP
AddressUnit: 8
Accessible over:
Group NOC.rcs__axi Mem with fixed address
| Address |
EndAddress |
Name |
Description |
| 0x00000000 |
|
DEVICE_ID_VENDOR_ID_REG |
Device ID , RCRB next offset pointer and Vendor ID Register. |
| 0x00000004 |
|
STATUS_COMMAND_REG |
Status and Command Register. |
| 0x00000008 |
|
CLASS_CODE_REVISION_ID |
Class Code and Revision ID Register. |
| 0x0000000c |
|
BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG |
BIST, Header Type, Latency Timer, and Cache Line Size Register. |
| 0x00000010 |
|
BAR0_REG |
BAR0 Register. |
| 0x00000014 |
|
BAR1_REG |
BAR1 Register. |
| 0x00000018 |
|
BAR2_REG |
BAR2 Register. |
| 0x0000001c |
|
BAR3_REG |
BAR3 Register. |
| 0x00000020 |
|
BAR4_REG |
BAR4 Register. |
| 0x00000024 |
|
BAR5_REG |
BAR5 Register. |
| 0x00000028 |
|
CARDBUS_CIS_PTR_REG |
CardBus CIS Pointer Register. |
| 0x0000002c |
|
SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG |
Subsystem ID and Subsystem Vendor ID Register. |
| 0x00000030 |
|
EXP_ROM_BASE_ADDR_REG |
Expansion ROM BAR Register. |
| 0x00000034 |
|
PCI_CAP_PTR_REG |
Capabilities Pointer Register. |
| 0x00000038 |
0x0000003b |
(Not allocated) |
|
| 0x0000003c |
|
MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG |
Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register. |
| 0x00000040 |
|
CAP_ID_NXT_PTR_REG |
Power Management Capabilities Register. |
| 0x00000044 |
|
CON_STATUS_REG |
Power Management Control and Status Register. |
| 0x00000048 |
0x0000004f |
(Not allocated) |
|
| 0x00000050 |
|
PCI_MSI_CAP_ID_NEXT_CTRL_REG |
MSI Capability Header and Message Control Register. |
| 0x00000054 |
|
MSI_CAP_OFF_04H_REG |
Message Address Register for MSI (Offset 04h). |
| 0x00000058 |
|
MSI_CAP_OFF_08H_REG |
Message Address Register for MSI (Offset 08h). |
| 0x0000005c |
|
MSI_CAP_OFF_0CH_REG |
Message Address Register for MSI (Offset 0Ch). |
| 0x00000060 |
|
MSI_CAP_OFF_10H_REG |
Message Address Register for MSI (Offset 10h). |
| 0x00000064 |
|
MSI_CAP_OFF_14H_REG |
Message Address Register for MSI (Offset 14h). |
| 0x00000068 |
0x0000006f |
(Not allocated) |
|
| 0x00000070 |
|
PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG |
PCI Express Capabilities, ID, Next Pointer Register. |
| 0x00000074 |
|
DEVICE_CAPABILITIES_REG |
Device Capabilities Register. |
| 0x00000078 |
|
DEVICE_CONTROL_DEVICE_STATUS |
Device Control and Device Status Register. |
| 0x0000007c |
|
LINK_CAPABILITIES_REG |
Link Capabilities Register. |
| 0x00000080 |
|
LINK_CONTROL_LINK_STATUS_REG |
Link Control and Link Status Register. |
| 0x00000084 |
0x00000093 |
(Not allocated) |
|
| 0x00000094 |
|
DEVICE_CAPABILITIES2_REG |
Device Capabilities 2 Register. |
| 0x00000098 |
|
DEVICE_CONTROL2_DEVICE_STATUS2_REG |
Device Control 2 and Status 2 Register. |
| 0x0000009c |
|
LINK_CAPABILITIES2_REG |
Link Capabilities 2 Register. |
| 0x000000a0 |
|
LINK_CONTROL2_LINK_STATUS2_REG |
Link Control 2 and Status 2 Register. |
| 0x000000a4 |
0x000000af |
(Not allocated) |
|
| 0x000000b0 |
|
PCI_MSIX_CAP_ID_NEXT_CTRL_REG |
MSI-X Capability ID, Next Pointer, Control Register. |
| 0x000000b4 |
|
MSIX_TABLE_OFFSET_REG |
MSI-X Table Offset and BIR Register. |
| 0x000000b8 |
|
MSIX_PBA_OFFSET_REG |
MSI-X PBA Offset and BIR Register. |
| 0x000000bc |
0x000000ff |
(Not allocated) |
|
| 0x00000100 |
|
AER_EXT_CAP_HDR_OFF |
Advanced Error Reporting Extended Capability Header. |
| 0x00000104 |
|
UNCORR_ERR_STATUS_OFF |
Uncorrectable Error Status Register. |
| 0x00000108 |
|
UNCORR_ERR_MASK_OFF |
Uncorrectable Error Mask Register. |
| 0x0000010c |
|
UNCORR_ERR_SEV_OFF |
Uncorrectable Error Severity Register. |
| 0x00000110 |
|
CORR_ERR_STATUS_OFF |
Correctable Error Status Register. |
| 0x00000114 |
|
CORR_ERR_MASK_OFF |
Correctable Error Mask Register. |
| 0x00000118 |
|
ADV_ERR_CAP_CTRL_OFF |
Advanced Error Capabilities and Control Register. |
| 0x0000011c |
|
HDR_LOG_0_OFF |
Header Log Register 0. |
| 0x00000120 |
|
HDR_LOG_1_OFF |
Header Log Register 1. |
| 0x00000124 |
|
HDR_LOG_2_OFF |
Header Log Register 2. |
| 0x00000128 |
|
HDR_LOG_3_OFF |
Header Log Register 3. |
| 0x0000012c |
0x00000137 |
(Not allocated) |
|
| 0x00000138 |
|
TLP_PREFIX_LOG_1_OFF |
TLP Prefix Log Register 1. |
| 0x0000013c |
|
TLP_PREFIX_LOG_2_OFF |
TLP Prefix Log Register 2. |
| 0x00000140 |
|
TLP_PREFIX_LOG_3_OFF |
TLP Prefix Log Register 3. |
| 0x00000144 |
|
TLP_PREFIX_LOG_4_OFF |
TLP Prefix Log Register 4. |
| 0x00000148 |
|
SPCIE_CAP_HEADER_REG |
SPCIE Capability Header. |
| 0x0000014c |
|
LINK_CONTROL3_REG |
Link Control 3 Register. |
| 0x00000150 |
|
LANE_ERR_STATUS_REG |
Lane Error Status Register. |
| 0x00000154 |
|
SPCIE_CAP_OFF_0CH_REG |
Lane Equalization Control Register for lanes 1 and 0. |
| 0x00000158 |
|
PL16G_EXT_CAP_HDR_REG |
Physical Layer 16.0 GT/s Extended Capability Header. |
| 0x0000015c |
|
PL16G_CAPABILITY_REG |
16.0 GT/s Capabilities Register. |
| 0x00000160 |
|
PL16G_CONTROL_REG |
16.0 GT/s Control Register. |
| 0x00000164 |
|
PL16G_STATUS_REG |
16.0 GT/s Status Register. |
| 0x00000168 |
|
PL16G_LC_DPAR_STATUS_REG |
16.0 GT/s Local Data Parity Mismatch Status Register. |
| 0x0000016c |
|
PL16G_FIRST_RETIMER_DPAR_STATUS_REG |
16.0 GT/s First Retimer Data Parity Mismatch Status Register. |
| 0x00000170 |
|
PL16G_SECOND_RETIMER_DPAR_STATUS_REG |
16.0 GT/s Second Retimer Data Parity Mismatch Status Register. |
| 0x00000174 |
0x00000177 |
(Not allocated) |
|
| 0x00000178 |
|
PL16G_CAP_OFF_20H_REG |
16.0 GT/s Lane Equalization Control Register for Lane 0-3. |
| 0x0000017c |
|
MARGIN_EXT_CAP_HDR_REG |
Margining Extended Capability Header. |
| 0x00000180 |
|
MARGIN_PORT_CAPABILITIES_STATUS_REG |
Margining Port Capabilities and Status Register. |
| 0x00000184 |
|
MARGIN_LANE_CNTRL_STATUS0_REG |
Margining Lane Control and Status Register for Lane 0. |
| 0x00000188 |
|
MARGIN_LANE_CNTRL_STATUS1_REG |
Margining Lane Control and Status Register for Lane 1. |
| 0x0000018c |
|
PL32G_EXT_CAP_HDR_REG |
Physical Layer 32.0 GT/s Extended Capability Header. |
| 0x00000190 |
|
PL32G_CAPABILITY_REG |
32.0 GT/s Capabilities Register. |
| 0x00000194 |
|
PL32G_CONTROL_REG |
32.0 GT/s Control Register. |
| 0x00000198 |
|
PL32G_STATUS_REG |
32.0 GT/s Status Register. |
| 0x0000019c |
|
PL32G_RCVD_MOD_TS_DATA1_REG |
Received Modified TS Data 1 Register. |
| 0x000001a0 |
|
PL32G_RCVD_MOD_TS_DATA2_REG |
Received Modified TS Data 2 Register. |
| 0x000001a4 |
|
PL32G_TX_MOD_TS_DATA1_REG |
Transmitted Modified TS Data 1 Register. |
| 0x000001a8 |
|
PL32G_TX_MOD_TS_DATA2_REG |
Transmitted Modified TS Data 2 Register. |
| 0x000001ac |
|
PL32G_CAP_OFF_20H_REG |
32.0 GT/s Lane Equalization Control Register for Lane 0-3. |
| 0x000001b0 |
|
RAS_DES_CAP_HEADER_REG |
Vendor-Specific Extended Capability Header. |
| 0x000001b4 |
|
VENDOR_SPECIFIC_HEADER_REG |
Vendor-Specific Header. |
| 0x000001b8 |
|
EVENT_COUNTER_CONTROL_REG |
Event Counter Control. |
| 0x000001bc |
|
EVENT_COUNTER_DATA_REG |
Event Counter Data. |
| 0x000001c0 |
0x000001df |
(Not allocated) |
|
| 0x000001e0 |
|
EINJ_ENABLE_REG |
Error Injection Enable. |
| 0x000001e4 |
|
EINJ0_CRC_REG |
Error Injection Control 0 (CRC Error). |
| 0x000001e8 |
|
EINJ1_SEQNUM_REG |
Error Injection Control 1 (Sequence Number Error). |
| 0x000001ec |
|
EINJ2_DLLP_REG |
Error Injection Control 2 (DLLP Error). |
| 0x000001f0 |
|
EINJ3_SYMBOL_REG |
Error Injection Control 3 (Symbol Error). |
| 0x000001f4 |
|
EINJ4_FC_REG |
Error Injection Control 4 (FC Credit Error). |
| 0x000001f8 |
|
EINJ5_SP_TLP_REG |
Error Injection Control 5 (Specific TLP Error). |
| 0x000001fc |
|
EINJ6_COMPARE_POINT_H0_REG |
Error Injection Control 6 (Compare Point Header DWORD #0). |
| 0x00000200 |
|
EINJ6_COMPARE_POINT_H1_REG |
Error Injection Control 6 (Compare Point Header DWORD #1). |
| 0x00000204 |
|
EINJ6_COMPARE_POINT_H2_REG |
Error Injection Control 6 (Compare Point Header DWORD #2). |
| 0x00000208 |
|
EINJ6_COMPARE_POINT_H3_REG |
Error Injection Control 6 (Compare Point Header DWORD #3). |
| 0x0000020c |
|
EINJ6_COMPARE_VALUE_H0_REG |
Error Injection Control 6 (Compare Value Header DWORD #0). |
| 0x00000210 |
|
EINJ6_COMPARE_VALUE_H1_REG |
Error Injection Control 6 (Compare Value Header DWORD #1). |
| 0x00000214 |
|
EINJ6_COMPARE_VALUE_H2_REG |
Error Injection Control 6 (Compare Value Header DWORD #2). |
| 0x00000218 |
|
EINJ6_COMPARE_VALUE_H3_REG |
Error Injection Control 6 (Compare Value Header DWORD #3). |
| 0x0000021c |
|
EINJ6_CHANGE_POINT_H0_REG |
Error Injection Control 6 (Change Point Header DWORD #0). |
| 0x00000220 |
|
EINJ6_CHANGE_POINT_H1_REG |
Error Injection Control 6 (Change Point Header DWORD #1). |
| 0x00000224 |
|
EINJ6_CHANGE_POINT_H2_REG |
Error Injection Control 6 (Change Point Header DWORD #2). |
| 0x00000228 |
|
EINJ6_CHANGE_POINT_H3_REG |
Error Injection Control 6 (Change Point Header DWORD #3). |
| 0x0000022c |
|
EINJ6_CHANGE_VALUE_H0_REG |
Error Injection Control 6 (Change Value Header DWORD #0). |
| 0x00000230 |
|
EINJ6_CHANGE_VALUE_H1_REG |
Error Injection Control 6 (Change Value Header DWORD #1). |
| 0x00000234 |
|
EINJ6_CHANGE_VALUE_H2_REG |
Error Injection Control 6 (Change Value Header DWORD #2). |
| 0x00000238 |
|
EINJ6_CHANGE_VALUE_H3_REG |
Error Injection Control 6 (Change Value Header DWORD #3). |
| 0x0000023c |
|
EINJ6_TLP_REG |
Error Injection Control 6 (Packet Error). |
| 0x00000240 |
0x0000024f |
(Not allocated) |
|
| 0x00000250 |
|
SD_CONTROL1_REG |
Silicon Debug Control 1. |
| 0x00000254 |
|
SD_CONTROL2_REG |
Silicon Debug Control 2. |
| 0x00000258 |
0x0000025f |
(Not allocated) |
|
| 0x00000260 |
|
SD_STATUS_L1LANE_REG |
Silicon Debug Status(Layer1 Per-lane). |
| 0x00000264 |
|
SD_STATUS_L1LTSSM_REG |
Silicon Debug Status(Layer1 LTSSM). |
| 0x00000268 |
|
SD_STATUS_PM_REG |
Silicon Debug Status(PM). |
| 0x0000026c |
|
SD_STATUS_L2_REG |
Silicon Debug Status(Layer2). |
| 0x00000270 |
|
SD_STATUS_L3FC_REG |
Silicon Debug Status(Layer3 FC). |
| 0x00000274 |
|
SD_STATUS_L3_REG |
Silicon Debug Status(Layer3). |
| 0x00000278 |
0x0000027f |
(Not allocated) |
|
| 0x00000280 |
|
SD_EQ_CONTROL1_REG |
Silicon Debug EQ Control 1. |
| 0x00000284 |
|
SD_EQ_CONTROL2_REG |
Silicon Debug EQ Control 2. |
| 0x00000288 |
|
SD_EQ_CONTROL3_REG |
Silicon Debug EQ Control 3. |
| 0x0000028c |
0x0000028f |
(Not allocated) |
|
| 0x00000290 |
|
SD_EQ_STATUS1_REG |
Silicon Debug EQ Status 1. |
| 0x00000294 |
|
SD_EQ_STATUS2_REG |
Silicon Debug EQ Status 2. |
| 0x00000298 |
|
SD_EQ_STATUS3_REG |
Silicon Debug EQ Status 3. |
| 0x0000029c |
0x000002af |
(Not allocated) |
|
| 0x000002b0 |
|
DATA_LINK_FEATURE_EXT_HDR_OFF |
Data Link Feature Extended Capability Header Register. |
| 0x000002b4 |
|
DATA_LINK_FEATURE_CAP_OFF |
Data Link Feature Capabilities Register. |
| 0x000002b8 |
|
DATA_LINK_FEATURE_STATUS_OFF |
Data Link Feature Status Register. |
| 0x000002bc |
|
VSECDMA_EXT_CAP_HDR_OFF |
PCIe Extended Capability ID, Capability Version, and Next Capability Offset Register. |
| 0x000002c0 |
|
VSECDMA_VENDOR_SPECIFIC_HDR_OFF |
Vendor Specific Header Register. |
| 0x000002c4 |
|
VSECDMA_DEVICE_INFORMATION_OFF |
DMA and related AXI Bridge Implementation Information. |
| 0x000002c8 |
|
VSECDMA_NUM_CHAN_OFF |
Number of Implemented Channels Register. |
| 0x000002cc |
|
VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF |
DMA Register Map Start Address Offset Low Register. |
| 0x000002d0 |
|
VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF |
DMA Register Map Start Address Offset High Register. |
| 0x000002d4 |
0x000006ff |
(Not allocated) |
|
| 0x00000700 |
|
ACK_LATENCY_TIMER_OFF |
Ack Latency Timer and Replay Timer Register. |
| 0x00000704 |
|
VENDOR_SPEC_DLLP_OFF |
Vendor Specific DLLP Register. |
| 0x00000708 |
|
PORT_FORCE_OFF |
Port Force Link Register. |
| 0x0000070c |
|
ACK_F_ASPM_CTRL_OFF |
Ack Frequency and L0-L1 ASPM Control Register. |
| 0x00000710 |
|
PORT_LINK_CTRL_OFF |
Port Link Control Register. |
| 0x00000714 |
|
LANE_SKEW_OFF |
Lane Skew Register. |
| 0x00000718 |
|
TIMER_CTRL_MAX_FUNC_NUM_OFF |
Timer Control and Max Function Number Register. |
| 0x0000071c |
|
SYMBOL_TIMER_FILTER_1_OFF |
Symbol Timer Register and Filter Mask 1 Register. |
| 0x00000720 |
|
FILTER_MASK_2_OFF |
Filter Mask 2 Register. |
| 0x00000724 |
0x00000727 |
(Not allocated) |
|
| 0x00000728 |
|
PL_DEBUG0_OFF |
Debug Register 0. |
| 0x0000072c |
|
PL_DEBUG1_OFF |
Debug Register 1. |
| 0x00000730 |
|
TX_P_FC_CREDIT_STATUS_OFF |
Transmit Posted FC Credit Status. |
| 0x00000734 |
|
TX_NP_FC_CREDIT_STATUS_OFF |
Transmit Non-Posted FC Credit Status. |
| 0x00000738 |
|
TX_CPL_FC_CREDIT_STATUS_OFF |
Transmit Completion FC Credit Status |
| 0x0000073c |
|
QUEUE_STATUS_OFF |
Queue Status. |
| 0x00000740 |
|
VC_TX_ARBI_1_OFF |
VC Transmit Arbitration Register 1. |
| 0x00000744 |
|
VC_TX_ARBI_2_OFF |
VC Transmit Arbitration Register 2. |
| 0x00000748 |
|
VC0_P_RX_Q_CTRL_OFF |
Segmented-Buffer VC0 Posted Receive Queue Control. |
| 0x0000074c |
|
VC0_NP_RX_Q_CTRL_OFF |
Segmented-Buffer VC0 Non-Posted Receive Queue Control. |
| 0x00000750 |
|
VC0_CPL_RX_Q_CTRL_OFF |
Segmented-Buffer VC0 Completion Receive Queue Control. |
| 0x00000754 |
0x0000080b |
(Not allocated) |
|
| 0x0000080c |
|
GEN2_CTRL_OFF |
Link Width and Speed Change Control Register. |
| 0x00000810 |
|
PHY_STATUS_OFF |
PHY Status Register. |
| 0x00000814 |
|
PHY_CONTROL_OFF |
PHY Control Register. |
| 0x00000818 |
0x0000081b |
(Not allocated) |
|
| 0x0000081c |
|
TRGT_MAP_CTRL_OFF |
Programmable Target Map Control Register. |
| 0x00000820 |
0x0000088b |
(Not allocated) |
|
| 0x0000088c |
|
CLOCK_GATING_CTRL_OFF |
Clock Gating Control Register. |
| 0x00000890 |
|
GEN3_RELATED_OFF |
Gen3 Control Register. |
| 0x00000894 |
|
GEN3_EQ_LOCAL_FS_LF_OFF |
Gen3 EQ FS and LF Register. |
| 0x00000898 |
|
GEN3_EQ_PSET_COEF_MAP__0 |
Gen3 EQ Presets to Coefficients Mapping Register. |
| 0x0000089c |
|
GEN3_EQ_PSET_INDEX_OFF |
Gen3 EQ Preset Index Register. |
| 0x000008a0 |
0x000008a3 |
(Not allocated) |
|
| 0x000008a4 |
|
GEN3_EQ_COEFF_LEGALITY_STATUS_OFF |
Gen3 EQ Status Register. |
| 0x000008a8 |
|
GEN3_EQ_CONTROL_OFF |
Gen3 EQ Control Register. |
| 0x000008ac |
0x000008b3 |
(Not allocated) |
|
| 0x000008b4 |
|
ORDER_RULE_CTRL_OFF |
Order Rule Control Register. |
| 0x000008b8 |
|
PIPE_LOOPBACK_CONTROL_OFF |
PIPE Loopback Control Register. |
| 0x000008bc |
|
MISC_CONTROL_1_OFF |
DBI Read-Only Write Enable Register. |
| 0x000008c0 |
|
MULTI_LANE_CONTROL_OFF |
UpConfigure Multi-lane Control Register. |
| 0x000008c4 |
|
PHY_INTEROP_CTRL_OFF |
PHY Interoperability Control Register. |
| 0x000008c8 |
|
TRGT_CPL_LUT_DELETE_ENTRY_OFF |
TRGT_CPL_LUT Delete Entry Control register. |
| 0x000008cc |
|
LINK_FLUSH_CONTROL_OFF |
Link Reset Request Flush Control Register. |
| 0x000008d0 |
|
AMBA_ERROR_RESPONSE_DEFAULT_OFF |
AXI Bridge Subordinate Error Response Register. |
| 0x000008d4 |
|
AMBA_LINK_TIMEOUT_OFF |
Link Down AXI Bridge Subordinate Timeout Register. |
| 0x000008d8 |
|
AMBA_ORDERING_CTRL_OFF |
AXI Bridge Ordering Control. |
| 0x000008dc |
0x000008df |
(Not allocated) |
|
| 0x000008e0 |
|
COHERENCY_CONTROL_1_OFF |
Cache Coherency Control Register 1. |
| 0x000008e4 |
0x000008e7 |
(Not allocated) |
|
| 0x000008e8 |
|
COHERENCY_CONTROL_3_OFF |
Cache Coherency Control Register 3. |
| 0x000008ec |
0x000008ef |
(Not allocated) |
|
| 0x000008f0 |
|
AXI_MSTR_MSG_ADDR_LOW_OFF |
Lower 32-bits of the Programmable AXI Address. |
| 0x000008f4 |
|
AXI_MSTR_MSG_ADDR_HIGH_OFF |
Upper 32-bits of the Programmable AXI Address. |
| 0x000008f8 |
|
PCIE_VERSION_NUMBER_OFF |
PCIe Controller IIP Release Version Number. |
| 0x000008fc |
|
PCIE_VERSION_TYPE_OFF |
PCIe Controller IIP Release Version Type. |
| 0x00000900 |
0x0000093f |
(Not allocated) |
|
| 0x00000940 |
|
MSIX_ADDRESS_MATCH_LOW_OFF |
MSI-X Address Match Low Register. |
| 0x00000944 |
|
MSIX_ADDRESS_MATCH_HIGH_OFF |
MSIX Address Match High Register. |
| 0x00000948 |
|
MSIX_DOORBELL_OFF |
MSI-X Doorbell Register. |
| 0x0000094c |
|
MSIX_RAM_CTRL_OFF |
MSI-X RAM power mode and debug control register. |
| 0x00000950 |
0x00000b0f |
(Not allocated) |
|
| 0x00000b10 |
|
PL_APP_BUS_DEV_NUM_STATUS_OFF |
Application driven bus and device number register. |
| 0x00000b14 |
0x00000b1b |
(Not allocated) |
|
| 0x00000b1c |
|
PCIPM_TRAFFIC_CTRL_OFF |
TLP Traffic during Non-D0 State Control Register. |
| 0x00000b20 |
0x00000b3f |
(Not allocated) |
|
| 0x00000b40 |
|
AUX_CLK_FREQ_OFF |
Auxiliary Clock Frequency Control Register. |
| 0x00000b44 |
0x00000b47 |
(Not allocated) |
|
| 0x00000b48 |
|
POWERDOWN_CTRL_STATUS_OFF |
Powerdown Control and Status Register. |
| 0x00000b4c |
|
PHY_INTEROP_CTRL_2_OFF |
PHY Interoperability Control 2 Register. |
| 0x00000b50 |
0x00000b7f |
(Not allocated) |
|
| 0x00000b80 |
|
GEN4_LANE_MARGINING_1_OFF |
Gen4 Lane Margining 1 Register. |
| 0x00000b84 |
|
GEN4_LANE_MARGINING_2_OFF |
Gen4 Lane Margining 2 Register. |
| 0x00000b88 |
|
GEN5_LANE_MARGINING_1_OFF |
Gen5 Lane Margining 1 Register. |
| 0x00000b8c |
|
GEN5_LANE_MARGINING_2_OFF |
Gen5 Lane Margining 2 Register. |
| 0x00000b90 |
|
PIPE_RELATED_OFF |
PIPE Related Register. |
| 0x00000b94 |
0x00000c7b |
(Not allocated) |
|
| 0x00000c7c |
|
DBI_FUNCTION_BANK_CTRL_REG_OFF |
DBI Function Bank Control Register. |
| 0x00000c80 |
|
UTILITY_OFF |
UTILITY register (Reserved). |
| 0x00000c84 |
0x00000c87 |
(Not allocated) |
|
| 0x00000c88 |
|
PM_UTILITY_OFF |
PM Shadow of UTILITY register (Reserved). |
| 0x00000c8c |
|
IDE_CTRL_OFF |
IDE Control register |
| 0x00000c90 |
0x00000cab |
(Not allocated) |
|
| 0x00000cac |
|
PRBS_LOOPBACK_TEST_REG_OFF |
PRBS Loopback Test Control Register. |
| 0x00000cb0 |
0x0010000f |
(Not allocated) |
|
| 0x00100010 |
|
BAR0_MASK_REG |
BAR$ Mask Register. |
| 0x00100014 |
|
BAR1_MASK_REG |
BAR1 Mask Register. |
| 0x00100018 |
|
BAR2_MASK_REG |
BAR2 Mask Register. |
| 0x0010001c |
|
BAR3_MASK_REG |
BAR3 Mask Register. |
| 0x00100020 |
|
BAR4_MASK_REG |
BAR4 Mask Register. |
| 0x00100024 |
|
BAR5_MASK_REG |
BAR5 Mask Register. |
| 0x00100028 |
0x0010002f |
(Not allocated) |
|
| 0x00100030 |
|
EXP_ROM_BAR_MASK_REG |
Expansion ROM BAR Mask Register. |
| 0x00100034 |
0x0010007b |
(Not allocated) |
|
| 0x0010007c |
|
SHADOW_LINK_CAPABILITIES_REG |
Shadow Link Capabilities Register. |
| 0x00100080 |
0x002fffff |
(Not allocated) |
|
| 0x00300000 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_0 |
iATU Region Control 1 Register. |
| 0x00300004 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_0 |
iATU Region Control 2 Register. |
| 0x00300008 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 |
iATU Lower Base Address Register. |
| 0x0030000c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 |
iATU Upper Base Address Register. |
| 0x00300010 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_0 |
iATU Limit Address Register. |
| 0x00300014 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 |
iATU Lower Target Address Register. |
| 0x00300018 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 |
iATU Upper Target Address Register. |
| 0x0030001c |
0x003000ff |
(Not allocated) |
|
| 0x00300100 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_0 |
iATU Region Control 1 Register. |
| 0x00300104 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_0 |
iATU Region Control 2 Register. |
| 0x00300108 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_0 |
iATU Lower Base Address Register. |
| 0x0030010c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_0 |
iATU Upper Base Address Register. |
| 0x00300110 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_0 |
iATU Limit Address Register. |
| 0x00300114 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 |
iATU Lower Target Address Register. |
| 0x00300118 |
0x003001ff |
(Not allocated) |
|
| 0x00300200 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_1 |
iATU Region Control 1 Register. |
| 0x00300204 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_1 |
iATU Region Control 2 Register. |
| 0x00300208 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1 |
iATU Lower Base Address Register. |
| 0x0030020c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1 |
iATU Upper Base Address Register. |
| 0x00300210 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_1 |
iATU Limit Address Register. |
| 0x00300214 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1 |
iATU Lower Target Address Register. |
| 0x00300218 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1 |
iATU Upper Target Address Register. |
| 0x0030021c |
0x003002ff |
(Not allocated) |
|
| 0x00300300 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_1 |
iATU Region Control 1 Register. |
| 0x00300304 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_1 |
iATU Region Control 2 Register. |
| 0x00300308 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_1 |
iATU Lower Base Address Register. |
| 0x0030030c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_1 |
iATU Upper Base Address Register. |
| 0x00300310 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_1 |
iATU Limit Address Register. |
| 0x00300314 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_1 |
iATU Lower Target Address Register. |
| 0x00300318 |
0x003003ff |
(Not allocated) |
|
| 0x00300400 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_2 |
iATU Region Control 1 Register. |
| 0x00300404 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_2 |
iATU Region Control 2 Register. |
| 0x00300408 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2 |
iATU Lower Base Address Register. |
| 0x0030040c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2 |
iATU Upper Base Address Register. |
| 0x00300410 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_2 |
iATU Limit Address Register. |
| 0x00300414 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2 |
iATU Lower Target Address Register. |
| 0x00300418 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2 |
iATU Upper Target Address Register. |
| 0x0030041c |
0x003004ff |
(Not allocated) |
|
| 0x00300500 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_2 |
iATU Region Control 1 Register. |
| 0x00300504 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_2 |
iATU Region Control 2 Register. |
| 0x00300508 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_2 |
iATU Lower Base Address Register. |
| 0x0030050c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_2 |
iATU Upper Base Address Register. |
| 0x00300510 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_2 |
iATU Limit Address Register. |
| 0x00300514 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_2 |
iATU Lower Target Address Register. |
| 0x00300518 |
0x003005ff |
(Not allocated) |
|
| 0x00300600 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_3 |
iATU Region Control 1 Register. |
| 0x00300604 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_3 |
iATU Region Control 2 Register. |
| 0x00300608 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3 |
iATU Lower Base Address Register. |
| 0x0030060c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3 |
iATU Upper Base Address Register. |
| 0x00300610 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_3 |
iATU Limit Address Register. |
| 0x00300614 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3 |
iATU Lower Target Address Register. |
| 0x00300618 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3 |
iATU Upper Target Address Register. |
| 0x0030061c |
0x003006ff |
(Not allocated) |
|
| 0x00300700 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_3 |
iATU Region Control 1 Register. |
| 0x00300704 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_3 |
iATU Region Control 2 Register. |
| 0x00300708 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_3 |
iATU Lower Base Address Register. |
| 0x0030070c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_3 |
iATU Upper Base Address Register. |
| 0x00300710 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_3 |
iATU Limit Address Register. |
| 0x00300714 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_3 |
iATU Lower Target Address Register. |
| 0x00300718 |
0x003007ff |
(Not allocated) |
|
| 0x00300800 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_4 |
iATU Region Control 1 Register. |
| 0x00300804 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_4 |
iATU Region Control 2 Register. |
| 0x00300808 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4 |
iATU Lower Base Address Register. |
| 0x0030080c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4 |
iATU Upper Base Address Register. |
| 0x00300810 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_4 |
iATU Limit Address Register. |
| 0x00300814 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4 |
iATU Lower Target Address Register. |
| 0x00300818 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4 |
iATU Upper Target Address Register. |
| 0x0030081c |
0x003008ff |
(Not allocated) |
|
| 0x00300900 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_4 |
iATU Region Control 1 Register. |
| 0x00300904 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_4 |
iATU Region Control 2 Register. |
| 0x00300908 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_4 |
iATU Lower Base Address Register. |
| 0x0030090c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_4 |
iATU Upper Base Address Register. |
| 0x00300910 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_4 |
iATU Limit Address Register. |
| 0x00300914 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_4 |
iATU Lower Target Address Register. |
| 0x00300918 |
0x003009ff |
(Not allocated) |
|
| 0x00300a00 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_5 |
iATU Region Control 1 Register. |
| 0x00300a04 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_5 |
iATU Region Control 2 Register. |
| 0x00300a08 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5 |
iATU Lower Base Address Register. |
| 0x00300a0c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5 |
iATU Upper Base Address Register. |
| 0x00300a10 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_5 |
iATU Limit Address Register. |
| 0x00300a14 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5 |
iATU Lower Target Address Register. |
| 0x00300a18 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5 |
iATU Upper Target Address Register. |
| 0x00300a1c |
0x00300aff |
(Not allocated) |
|
| 0x00300b00 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_5 |
iATU Region Control 1 Register. |
| 0x00300b04 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_5 |
iATU Region Control 2 Register. |
| 0x00300b08 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_5 |
iATU Lower Base Address Register. |
| 0x00300b0c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_5 |
iATU Upper Base Address Register. |
| 0x00300b10 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_5 |
iATU Limit Address Register. |
| 0x00300b14 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_5 |
iATU Lower Target Address Register. |
| 0x00300b18 |
0x00300bff |
(Not allocated) |
|
| 0x00300c00 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_6 |
iATU Region Control 1 Register. |
| 0x00300c04 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_6 |
iATU Region Control 2 Register. |
| 0x00300c08 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6 |
iATU Lower Base Address Register. |
| 0x00300c0c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6 |
iATU Upper Base Address Register. |
| 0x00300c10 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_6 |
iATU Limit Address Register. |
| 0x00300c14 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6 |
iATU Lower Target Address Register. |
| 0x00300c18 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6 |
iATU Upper Target Address Register. |
| 0x00300c1c |
0x00300cff |
(Not allocated) |
|
| 0x00300d00 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_6 |
iATU Region Control 1 Register. |
| 0x00300d04 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_6 |
iATU Region Control 2 Register. |
| 0x00300d08 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_6 |
iATU Lower Base Address Register. |
| 0x00300d0c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_6 |
iATU Upper Base Address Register. |
| 0x00300d10 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_6 |
iATU Limit Address Register. |
| 0x00300d14 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_6 |
iATU Lower Target Address Register. |
| 0x00300d18 |
0x00300dff |
(Not allocated) |
|
| 0x00300e00 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_7 |
iATU Region Control 1 Register. |
| 0x00300e04 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_7 |
iATU Region Control 2 Register. |
| 0x00300e08 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7 |
iATU Lower Base Address Register. |
| 0x00300e0c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7 |
iATU Upper Base Address Register. |
| 0x00300e10 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_7 |
iATU Limit Address Register. |
| 0x00300e14 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7 |
iATU Lower Target Address Register. |
| 0x00300e18 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7 |
iATU Upper Target Address Register. |
| 0x00300e1c |
0x00300eff |
(Not allocated) |
|
| 0x00300f00 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_7 |
iATU Region Control 1 Register. |
| 0x00300f04 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_7 |
iATU Region Control 2 Register. |
| 0x00300f08 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_7 |
iATU Lower Base Address Register. |
| 0x00300f0c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_7 |
iATU Upper Base Address Register. |
| 0x00300f10 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_7 |
iATU Limit Address Register. |
| 0x00300f14 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_7 |
iATU Lower Target Address Register. |
| 0x00300f18 |
0x00300fff |
(Not allocated) |
|
| 0x00301000 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_8 |
iATU Region Control 1 Register. |
| 0x00301004 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_8 |
iATU Region Control 2 Register. |
| 0x00301008 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8 |
iATU Lower Base Address Register. |
| 0x0030100c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8 |
iATU Upper Base Address Register. |
| 0x00301010 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_8 |
iATU Limit Address Register. |
| 0x00301014 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8 |
iATU Lower Target Address Register. |
| 0x00301018 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8 |
iATU Upper Target Address Register. |
| 0x0030101c |
0x003010ff |
(Not allocated) |
|
| 0x00301100 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_8 |
iATU Region Control 1 Register. |
| 0x00301104 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_8 |
iATU Region Control 2 Register. |
| 0x00301108 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_8 |
iATU Lower Base Address Register. |
| 0x0030110c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_8 |
iATU Upper Base Address Register. |
| 0x00301110 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_8 |
iATU Limit Address Register. |
| 0x00301114 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_8 |
iATU Lower Target Address Register. |
| 0x00301118 |
0x003011ff |
(Not allocated) |
|
| 0x00301200 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_9 |
iATU Region Control 1 Register. |
| 0x00301204 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_9 |
iATU Region Control 2 Register. |
| 0x00301208 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9 |
iATU Lower Base Address Register. |
| 0x0030120c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9 |
iATU Upper Base Address Register. |
| 0x00301210 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_9 |
iATU Limit Address Register. |
| 0x00301214 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9 |
iATU Lower Target Address Register. |
| 0x00301218 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9 |
iATU Upper Target Address Register. |
| 0x0030121c |
0x003012ff |
(Not allocated) |
|
| 0x00301300 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_9 |
iATU Region Control 1 Register. |
| 0x00301304 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_9 |
iATU Region Control 2 Register. |
| 0x00301308 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_9 |
iATU Lower Base Address Register. |
| 0x0030130c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_9 |
iATU Upper Base Address Register. |
| 0x00301310 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_9 |
iATU Limit Address Register. |
| 0x00301314 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_9 |
iATU Lower Target Address Register. |
| 0x00301318 |
0x003013ff |
(Not allocated) |
|
| 0x00301400 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_10 |
iATU Region Control 1 Register. |
| 0x00301404 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_10 |
iATU Region Control 2 Register. |
| 0x00301408 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10 |
iATU Lower Base Address Register. |
| 0x0030140c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10 |
iATU Upper Base Address Register. |
| 0x00301410 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_10 |
iATU Limit Address Register. |
| 0x00301414 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10 |
iATU Lower Target Address Register. |
| 0x00301418 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10 |
iATU Upper Target Address Register. |
| 0x0030141c |
0x003014ff |
(Not allocated) |
|
| 0x00301500 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_10 |
iATU Region Control 1 Register. |
| 0x00301504 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_10 |
iATU Region Control 2 Register. |
| 0x00301508 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_10 |
iATU Lower Base Address Register. |
| 0x0030150c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_10 |
iATU Upper Base Address Register. |
| 0x00301510 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_10 |
iATU Limit Address Register. |
| 0x00301514 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_10 |
iATU Lower Target Address Register. |
| 0x00301518 |
0x003015ff |
(Not allocated) |
|
| 0x00301600 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_11 |
iATU Region Control 1 Register. |
| 0x00301604 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_11 |
iATU Region Control 2 Register. |
| 0x00301608 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11 |
iATU Lower Base Address Register. |
| 0x0030160c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11 |
iATU Upper Base Address Register. |
| 0x00301610 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_11 |
iATU Limit Address Register. |
| 0x00301614 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11 |
iATU Lower Target Address Register. |
| 0x00301618 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11 |
iATU Upper Target Address Register. |
| 0x0030161c |
0x003016ff |
(Not allocated) |
|
| 0x00301700 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_11 |
iATU Region Control 1 Register. |
| 0x00301704 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_11 |
iATU Region Control 2 Register. |
| 0x00301708 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_11 |
iATU Lower Base Address Register. |
| 0x0030170c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_11 |
iATU Upper Base Address Register. |
| 0x00301710 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_11 |
iATU Limit Address Register. |
| 0x00301714 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_11 |
iATU Lower Target Address Register. |
| 0x00301718 |
0x003017ff |
(Not allocated) |
|
| 0x00301800 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_12 |
iATU Region Control 1 Register. |
| 0x00301804 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_12 |
iATU Region Control 2 Register. |
| 0x00301808 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12 |
iATU Lower Base Address Register. |
| 0x0030180c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12 |
iATU Upper Base Address Register. |
| 0x00301810 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_12 |
iATU Limit Address Register. |
| 0x00301814 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12 |
iATU Lower Target Address Register. |
| 0x00301818 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12 |
iATU Upper Target Address Register. |
| 0x0030181c |
0x003018ff |
(Not allocated) |
|
| 0x00301900 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_12 |
iATU Region Control 1 Register. |
| 0x00301904 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_12 |
iATU Region Control 2 Register. |
| 0x00301908 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_12 |
iATU Lower Base Address Register. |
| 0x0030190c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_12 |
iATU Upper Base Address Register. |
| 0x00301910 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_12 |
iATU Limit Address Register. |
| 0x00301914 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_12 |
iATU Lower Target Address Register. |
| 0x00301918 |
0x003019ff |
(Not allocated) |
|
| 0x00301a00 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_13 |
iATU Region Control 1 Register. |
| 0x00301a04 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_13 |
iATU Region Control 2 Register. |
| 0x00301a08 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13 |
iATU Lower Base Address Register. |
| 0x00301a0c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13 |
iATU Upper Base Address Register. |
| 0x00301a10 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_13 |
iATU Limit Address Register. |
| 0x00301a14 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13 |
iATU Lower Target Address Register. |
| 0x00301a18 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13 |
iATU Upper Target Address Register. |
| 0x00301a1c |
0x00301aff |
(Not allocated) |
|
| 0x00301b00 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_13 |
iATU Region Control 1 Register. |
| 0x00301b04 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_13 |
iATU Region Control 2 Register. |
| 0x00301b08 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_13 |
iATU Lower Base Address Register. |
| 0x00301b0c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_13 |
iATU Upper Base Address Register. |
| 0x00301b10 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_13 |
iATU Limit Address Register. |
| 0x00301b14 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_13 |
iATU Lower Target Address Register. |
| 0x00301b18 |
0x00301bff |
(Not allocated) |
|
| 0x00301c00 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_14 |
iATU Region Control 1 Register. |
| 0x00301c04 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_14 |
iATU Region Control 2 Register. |
| 0x00301c08 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14 |
iATU Lower Base Address Register. |
| 0x00301c0c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14 |
iATU Upper Base Address Register. |
| 0x00301c10 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_14 |
iATU Limit Address Register. |
| 0x00301c14 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14 |
iATU Lower Target Address Register. |
| 0x00301c18 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14 |
iATU Upper Target Address Register. |
| 0x00301c1c |
0x00301cff |
(Not allocated) |
|
| 0x00301d00 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_14 |
iATU Region Control 1 Register. |
| 0x00301d04 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_14 |
iATU Region Control 2 Register. |
| 0x00301d08 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_14 |
iATU Lower Base Address Register. |
| 0x00301d0c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_14 |
iATU Upper Base Address Register. |
| 0x00301d10 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_14 |
iATU Limit Address Register. |
| 0x00301d14 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_14 |
iATU Lower Target Address Register. |
| 0x00301d18 |
0x00301dff |
(Not allocated) |
|
| 0x00301e00 |
|
IATU_REGION_CTRL_1_OFF_OUTBOUND_15 |
iATU Region Control 1 Register. |
| 0x00301e04 |
|
IATU_REGION_CTRL_2_OFF_OUTBOUND_15 |
iATU Region Control 2 Register. |
| 0x00301e08 |
|
IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15 |
iATU Lower Base Address Register. |
| 0x00301e0c |
|
IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15 |
iATU Upper Base Address Register. |
| 0x00301e10 |
|
IATU_LIMIT_ADDR_OFF_OUTBOUND_15 |
iATU Limit Address Register. |
| 0x00301e14 |
|
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15 |
iATU Lower Target Address Register. |
| 0x00301e18 |
|
IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15 |
iATU Upper Target Address Register. |
| 0x00301e1c |
0x00301eff |
(Not allocated) |
|
| 0x00301f00 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_15 |
iATU Region Control 1 Register. |
| 0x00301f04 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_15 |
iATU Region Control 2 Register. |
| 0x00301f08 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_15 |
iATU Lower Base Address Register. |
| 0x00301f0c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_15 |
iATU Upper Base Address Register. |
| 0x00301f10 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_15 |
iATU Limit Address Register. |
| 0x00301f14 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_15 |
iATU Lower Target Address Register. |
| 0x00301f18 |
0x003020ff |
(Not allocated) |
|
| 0x00302100 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_16 |
iATU Region Control 1 Register. |
| 0x00302104 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_16 |
iATU Region Control 2 Register. |
| 0x00302108 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_16 |
iATU Lower Base Address Register. |
| 0x0030210c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_16 |
iATU Upper Base Address Register. |
| 0x00302110 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_16 |
iATU Limit Address Register. |
| 0x00302114 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_16 |
iATU Lower Target Address Register. |
| 0x00302118 |
0x003022ff |
(Not allocated) |
|
| 0x00302300 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_17 |
iATU Region Control 1 Register. |
| 0x00302304 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_17 |
iATU Region Control 2 Register. |
| 0x00302308 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_17 |
iATU Lower Base Address Register. |
| 0x0030230c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_17 |
iATU Upper Base Address Register. |
| 0x00302310 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_17 |
iATU Limit Address Register. |
| 0x00302314 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_17 |
iATU Lower Target Address Register. |
| 0x00302318 |
0x003024ff |
(Not allocated) |
|
| 0x00302500 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_18 |
iATU Region Control 1 Register. |
| 0x00302504 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_18 |
iATU Region Control 2 Register. |
| 0x00302508 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_18 |
iATU Lower Base Address Register. |
| 0x0030250c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_18 |
iATU Upper Base Address Register. |
| 0x00302510 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_18 |
iATU Limit Address Register. |
| 0x00302514 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_18 |
iATU Lower Target Address Register. |
| 0x00302518 |
0x003026ff |
(Not allocated) |
|
| 0x00302700 |
|
IATU_REGION_CTRL_1_OFF_INBOUND_19 |
iATU Region Control 1 Register. |
| 0x00302704 |
|
IATU_REGION_CTRL_2_OFF_INBOUND_19 |
iATU Region Control 2 Register. |
| 0x00302708 |
|
IATU_LWR_BASE_ADDR_OFF_INBOUND_19 |
iATU Lower Base Address Register. |
| 0x0030270c |
|
IATU_UPPER_BASE_ADDR_OFF_INBOUND_19 |
iATU Upper Base Address Register. |
| 0x00302710 |
|
IATU_LIMIT_ADDR_OFF_INBOUND_19 |
iATU Limit Address Register. |
| 0x00302714 |
|
IATU_LWR_TARGET_ADDR_OFF_INBOUND_19 |
iATU Lower Target Address Register. |
| 0x00302718 |
0x0037ffff |
(Not allocated) |
|
| 0x00380000 |
|
HDMA_EN_OFF_WRCH_0 |
HDMA Write Channel Enable Register. |
| 0x00380004 |
|
HDMA_DOORBELL_OFF_WRCH_0 |
HDMA Write Channel Doorbell Register. |
| 0x00380008 |
|
HDMA_ELEM_PF_OFF_WRCH_0 |
HDMA Write Channel Prefetch Register. |
| 0x0038000c |
0x0038000f |
(Not allocated) |
|
| 0x00380010 |
|
HDMA_LLP_LOW_OFF_WRCH_0 |
HDMA Write Channel Linked List Pointer Low Register. |
| 0x00380014 |
|
HDMA_LLP_HIGH_OFF_WRCH_0 |
HDMA Write Channel Linked List Pointer High Register. |
| 0x00380018 |
|
HDMA_CYCLE_OFF_WRCH_0 |
HDMA Write Channel Producer-Consumer Cycle Synchronization Register. |
| 0x0038001c |
|
HDMA_XFERSIZE_OFF_WRCH_0 |
HDMA Write Channel Transfer Size Register. |
| 0x00380020 |
|
HDMA_SAR_LOW_OFF_WRCH_0 |
HDMA Write Channel SAR Low Register. |
| 0x00380024 |
|
HDMA_SAR_HIGH_OFF_WRCH_0 |
HDMA Write Channel SAR High Register. |
| 0x00380028 |
|
HDMA_DAR_LOW_OFF_WRCH_0 |
HDMA Write Channel DAR Low Register. |
| 0x0038002c |
|
HDMA_DAR_HIGH_OFF_WRCH_0 |
HDMA Write Channel DAR High Register. |
| 0x00380030 |
|
HDMA_WATERMARK_EN_OFF_WRCH_0 |
HDMA Write Channel Linked-list Watermark Enable Register. |
| 0x00380034 |
|
HDMA_CONTROL1_OFF_WRCH_0 |
HDMA Write Channel Control Settings 1 Register. |
| 0x00380038 |
|
HDMA_FUNC_NUM_OFF_WRCH_0 |
HDMA Write Channel Function Number Register. |
| 0x0038003c |
|
HDMA_QOS_OFF_WRCH_0 |
HDMA Write Channel QoS Settings Register. |
| 0x00380040 |
0x0038007f |
(Not allocated) |
|
| 0x00380080 |
|
HDMA_STATUS_OFF_WRCH_0 |
HDMA Write Channel Status Register. |
| 0x00380084 |
|
HDMA_INT_STATUS_OFF_WRCH_0 |
HDMA Write Channel Interrupt Status Register. |
| 0x00380088 |
|
HDMA_INT_SETUP_OFF_WRCH_0 |
HDMA Write Channel Interrupt Setup Register. |
| 0x0038008c |
|
HDMA_INT_CLEAR_OFF_WRCH_0 |
HDMA Write Channel Interrupt Clear Register. |
| 0x00380090 |
|
HDMA_MSI_STOP_LOW_OFF_WRCH_0 |
HDMA Write Stop Remote Interrupt Address Low Register. |
| 0x00380094 |
|
HDMA_MSI_STOP_HIGH_OFF_WRCH_0 |
HDMA Write Stop Remote Interrupt Address High Register. |
| 0x00380098 |
|
HDMA_MSI_WATERMARK_LOW_OFF_WRCH_0 |
HDMA Write Watermark Remote Interrupt Address Low Register. |
| 0x0038009c |
|
HDMA_MSI_WATERMARK_HIGH_OFF_WRCH_0 |
HDMA Write Watermark Remote Interrupt Address High Register. |
| 0x003800a0 |
|
HDMA_MSI_ABORT_LOW_OFF_WRCH_0 |
HDMA Write Abort Remote Interrupt Address Low Register. |
| 0x003800a4 |
|
HDMA_MSI_ABORT_HIGH_OFF_WRCH_0 |
HDMA Write Abort Remote Interrupt Address High Register. |
| 0x003800a8 |
|
HDMA_MSI_MSGD_OFF_WRCH_0 |
HDMA Write Channel Remote Interrupt Data Register. |
| 0x003800ac |
0x003800ff |
(Not allocated) |
|
| 0x00380100 |
|
HDMA_EN_OFF_RDCH_0 |
HDMA Read Channel Enable. |
| 0x00380104 |
|
HDMA_DOORBELL_OFF_RDCH_0 |
HDMA Read Channel Doorbell Register. |
| 0x00380108 |
|
HDMA_ELEM_PF_OFF_RDCH_0 |
HDMA Read Channel Prefetch Register. |
| 0x0038010c |
0x0038010f |
(Not allocated) |
|
| 0x00380110 |
|
HDMA_LLP_LOW_OFF_RDCH_0 |
HDMA Read Channel Linked List Pointer Low Register. |
| 0x00380114 |
|
HDMA_LLP_HIGH_OFF_RDCH_0 |
HDMA Read Channel Linked List Pointer High Register. |
| 0x00380118 |
|
HDMA_CYCLE_OFF_RDCH_0 |
HDMA Read Channel Producer-Consumer Cycle Synchronization Register. |
| 0x0038011c |
|
HDMA_XFERSIZE_OFF_RDCH_0 |
HDMA Read Channel Transfer Size Register. |
| 0x00380120 |
|
HDMA_SAR_LOW_OFF_RDCH_0 |
HDMA Read Channel SAR Low Register. |
| 0x00380124 |
|
HDMA_SAR_HIGH_OFF_RDCH_0 |
HDMA Read Channel SAR High Register. |
| 0x00380128 |
|
HDMA_DAR_LOW_OFF_RDCH_0 |
HDMA Read Channel DAR Low Register. |
| 0x0038012c |
|
HDMA_DAR_HIGH_OFF_RDCH_0 |
HDMA Read Channel DAR High Register. |
| 0x00380130 |
|
HDMA_WATERMARK_EN_OFF_RDCH_0 |
HDMA Read Channel Linked-list Watermark Enable Register. |
| 0x00380134 |
|
HDMA_CONTROL1_OFF_RDCH_0 |
HDMA Read Channel Control Settings 1 Register. |
| 0x00380138 |
|
HDMA_FUNC_NUM_OFF_RDCH_0 |
HDMA Read Channel Function Number Register. |
| 0x0038013c |
|
HDMA_QOS_OFF_RDCH_0 |
HDMA Read Channel QoS Settings Register. |
| 0x00380140 |
0x0038017f |
(Not allocated) |
|
| 0x00380180 |
|
HDMA_STATUS_OFF_RDCH_0 |
HDMA Read Channel Status Register. |
| 0x00380184 |
|
HDMA_INT_STATUS_OFF_RDCH_0 |
HDMA Read Channel Interrupt Status Register. |
| 0x00380188 |
|
HDMA_INT_SETUP_OFF_RDCH_0 |
HDMA Read Channel Interrupt Setup Register. |
| 0x0038018c |
|
HDMA_INT_CLEAR_OFF_RDCH_0 |
HDMA Read Channel Interrupt Clear Register. |
| 0x00380190 |
|
HDMA_MSI_STOP_LOW_OFF_RDCH_0 |
HDMA Read Stop Remote Interrupt Address Low Register. |
| 0x00380194 |
|
HDMA_MSI_STOP_HIGH_OFF_RDCH_0 |
HDMA Read Stop Remote Interrupt Address High Register. |
| 0x00380198 |
|
HDMA_MSI_WATERMARK_LOW_OFF_RDCH_0 |
HDMA Read Watermark Remote Interrupt Address Low Register. |
| 0x0038019c |
|
HDMA_MSI_WATERMARK_HIGH_OFF_RDCH_0 |
HDMA Read Watermark Remote Interrupt Address High Register. |
| 0x003801a0 |
|
HDMA_MSI_ABORT_LOW_OFF_RDCH_0 |
HDMA Read Abort Remote Interrupt Address Low Register. |
| 0x003801a4 |
|
HDMA_MSI_ABORT_HIGH_OFF_RDCH_0 |
HDMA Read Abort Remote Interrupt Address High. |
| 0x003801a8 |
|
HDMA_MSI_MSGD_OFF_RDCH_0 |
HDMA Read Channel Remote Interrupt Data Register. |
| 0x003801ac |
0x003801ff |
(Not allocated) |
|
| 0x00380200 |
|
HDMA_EN_OFF_WRCH_1 |
HDMA Write Channel Enable Register. |
| 0x00380204 |
|
HDMA_DOORBELL_OFF_WRCH_1 |
HDMA Write Channel Doorbell Register. |
| 0x00380208 |
|
HDMA_ELEM_PF_OFF_WRCH_1 |
HDMA Write Channel Prefetch Register. |
| 0x0038020c |
0x0038020f |
(Not allocated) |
|
| 0x00380210 |
|
HDMA_LLP_LOW_OFF_WRCH_1 |
HDMA Write Channel Linked List Pointer Low Register. |
| 0x00380214 |
|
HDMA_LLP_HIGH_OFF_WRCH_1 |
HDMA Write Channel Linked List Pointer High Register. |
| 0x00380218 |
|
HDMA_CYCLE_OFF_WRCH_1 |
HDMA Write Channel Producer-Consumer Cycle Synchronization Register. |
| 0x0038021c |
|
HDMA_XFERSIZE_OFF_WRCH_1 |
HDMA Write Channel Transfer Size Register. |
| 0x00380220 |
|
HDMA_SAR_LOW_OFF_WRCH_1 |
HDMA Write Channel SAR Low Register. |
| 0x00380224 |
|
HDMA_SAR_HIGH_OFF_WRCH_1 |
HDMA Write Channel SAR High Register. |
| 0x00380228 |
|
HDMA_DAR_LOW_OFF_WRCH_1 |
HDMA Write Channel DAR Low Register. |
| 0x0038022c |
|
HDMA_DAR_HIGH_OFF_WRCH_1 |
HDMA Write Channel DAR High Register. |
| 0x00380230 |
|
HDMA_WATERMARK_EN_OFF_WRCH_1 |
HDMA Write Channel Linked-list Watermark Enable Register. |
| 0x00380234 |
|
HDMA_CONTROL1_OFF_WRCH_1 |
HDMA Write Channel Control Settings 1 Register. |
| 0x00380238 |
|
HDMA_FUNC_NUM_OFF_WRCH_1 |
HDMA Write Channel Function Number Register. |
| 0x0038023c |
|
HDMA_QOS_OFF_WRCH_1 |
HDMA Write Channel QoS Settings Register. |
| 0x00380240 |
0x0038027f |
(Not allocated) |
|
| 0x00380280 |
|
HDMA_STATUS_OFF_WRCH_1 |
HDMA Write Channel Status Register. |
| 0x00380284 |
|
HDMA_INT_STATUS_OFF_WRCH_1 |
HDMA Write Channel Interrupt Status Register. |
| 0x00380288 |
|
HDMA_INT_SETUP_OFF_WRCH_1 |
HDMA Write Channel Interrupt Setup Register. |
| 0x0038028c |
|
HDMA_INT_CLEAR_OFF_WRCH_1 |
HDMA Write Channel Interrupt Clear Register. |
| 0x00380290 |
|
HDMA_MSI_STOP_LOW_OFF_WRCH_1 |
HDMA Write Stop Remote Interrupt Address Low Register. |
| 0x00380294 |
|
HDMA_MSI_STOP_HIGH_OFF_WRCH_1 |
HDMA Write Stop Remote Interrupt Address High Register. |
| 0x00380298 |
|
HDMA_MSI_WATERMARK_LOW_OFF_WRCH_1 |
HDMA Write Watermark Remote Interrupt Address Low Register. |
| 0x0038029c |
|
HDMA_MSI_WATERMARK_HIGH_OFF_WRCH_1 |
HDMA Write Watermark Remote Interrupt Address High Register. |
| 0x003802a0 |
|
HDMA_MSI_ABORT_LOW_OFF_WRCH_1 |
HDMA Write Abort Remote Interrupt Address Low Register. |
| 0x003802a4 |
|
HDMA_MSI_ABORT_HIGH_OFF_WRCH_1 |
HDMA Write Abort Remote Interrupt Address High Register. |
| 0x003802a8 |
|
HDMA_MSI_MSGD_OFF_WRCH_1 |
HDMA Write Channel Remote Interrupt Data Register. |
| 0x003802ac |
0x003802ff |
(Not allocated) |
|
| 0x00380300 |
|
HDMA_EN_OFF_RDCH_1 |
HDMA Read Channel Enable. |
| 0x00380304 |
|
HDMA_DOORBELL_OFF_RDCH_1 |
HDMA Read Channel Doorbell Register. |
| 0x00380308 |
|
HDMA_ELEM_PF_OFF_RDCH_1 |
HDMA Read Channel Prefetch Register. |
| 0x0038030c |
0x0038030f |
(Not allocated) |
|
| 0x00380310 |
|
HDMA_LLP_LOW_OFF_RDCH_1 |
HDMA Read Channel Linked List Pointer Low Register. |
| 0x00380314 |
|
HDMA_LLP_HIGH_OFF_RDCH_1 |
HDMA Read Channel Linked List Pointer High Register. |
| 0x00380318 |
|
HDMA_CYCLE_OFF_RDCH_1 |
HDMA Read Channel Producer-Consumer Cycle Synchronization Register. |
| 0x0038031c |
|
HDMA_XFERSIZE_OFF_RDCH_1 |
HDMA Read Channel Transfer Size Register. |
| 0x00380320 |
|
HDMA_SAR_LOW_OFF_RDCH_1 |
HDMA Read Channel SAR Low Register. |
| 0x00380324 |
|
HDMA_SAR_HIGH_OFF_RDCH_1 |
HDMA Read Channel SAR High Register. |
| 0x00380328 |
|
HDMA_DAR_LOW_OFF_RDCH_1 |
HDMA Read Channel DAR Low Register. |
| 0x0038032c |
|
HDMA_DAR_HIGH_OFF_RDCH_1 |
HDMA Read Channel DAR High Register. |
| 0x00380330 |
|
HDMA_WATERMARK_EN_OFF_RDCH_1 |
HDMA Read Channel Linked-list Watermark Enable Register. |
| 0x00380334 |
|
HDMA_CONTROL1_OFF_RDCH_1 |
HDMA Read Channel Control Settings 1 Register. |
| 0x00380338 |
|
HDMA_FUNC_NUM_OFF_RDCH_1 |
HDMA Read Channel Function Number Register. |
| 0x0038033c |
|
HDMA_QOS_OFF_RDCH_1 |
HDMA Read Channel QoS Settings Register. |
| 0x00380340 |
0x0038037f |
(Not allocated) |
|
| 0x00380380 |
|
HDMA_STATUS_OFF_RDCH_1 |
HDMA Read Channel Status Register. |
| 0x00380384 |
|
HDMA_INT_STATUS_OFF_RDCH_1 |
HDMA Read Channel Interrupt Status Register. |
| 0x00380388 |
|
HDMA_INT_SETUP_OFF_RDCH_1 |
HDMA Read Channel Interrupt Setup Register. |
| 0x0038038c |
|
HDMA_INT_CLEAR_OFF_RDCH_1 |
HDMA Read Channel Interrupt Clear Register. |
| 0x00380390 |
|
HDMA_MSI_STOP_LOW_OFF_RDCH_1 |
HDMA Read Stop Remote Interrupt Address Low Register. |
| 0x00380394 |
|
HDMA_MSI_STOP_HIGH_OFF_RDCH_1 |
HDMA Read Stop Remote Interrupt Address High Register. |
| 0x00380398 |
|
HDMA_MSI_WATERMARK_LOW_OFF_RDCH_1 |
HDMA Read Watermark Remote Interrupt Address Low Register. |
| 0x0038039c |
|
HDMA_MSI_WATERMARK_HIGH_OFF_RDCH_1 |
HDMA Read Watermark Remote Interrupt Address High Register. |
| 0x003803a0 |
|
HDMA_MSI_ABORT_LOW_OFF_RDCH_1 |
HDMA Read Abort Remote Interrupt Address Low Register. |
| 0x003803a4 |
|
HDMA_MSI_ABORT_HIGH_OFF_RDCH_1 |
HDMA Read Abort Remote Interrupt Address High. |
| 0x003803a8 |
|
HDMA_MSI_MSGD_OFF_RDCH_1 |
HDMA Read Channel Remote Interrupt Data Register. |
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Register Details for AddressMap abc_soc_top/dlnk/pcieabc78/DWC_pcie_dbi/DWC_PCIE_USP
Note: AddressOffsets before register name are offsets inside AddressMap (that is what the "+" means)
+0x00000000 Register(32 bit) DEVICE_ID_VENDOR_ID_REG
Device ID , RCRB next offset pointer and Vendor ID Register.
This register holds the device ID, next offset pointer for RCRB mode and vendor ID.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000000 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0dd68086 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
| Name |
PCI_TYPE0_DEVICE_ID |
PCI_TYPE0_VENDOR_ID |
| Access |
RO |
RO |
[31:16] RO |
PCI_TYPE0_DEVICE_ID
- DEVICE_ID [31:16] - The Device ID register identifies the particular Function for PCIe Type0 and Type1 configuration header. This identifier is allocated by the vendor. Databook.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0dd6;
|
[15:00] RO |
PCI_TYPE0_VENDOR_ID
Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x8086;
|
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+0x00000004 Register(32 bit) STATUS_COMMAND_REG
Status and Command Register.
This register provides the status and controls the behavior of a function.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000004 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00100000 |
|
|
Unaffected |
0x00090000 |
|
|
Undefined |
0x00010000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DETECTED_PARITY_ERR |
SIGNALED_SYS_ERR |
RCVD_MASTER_ABORT |
RCVD_TARGET_ABORT |
SIGNALED_TARGET_ABORT |
DEV_SEL_TIMING |
MASTER_DPE |
FAST_B2B_CAP |
RSVDP_22 |
FAST_66MHZ_CAP |
CAP_LIST |
INT_STATUS |
RSVDP_17 |
- |
PCI_TYPE_RESERV |
PCI_TYPE0_INT_EN |
RSVDP_9 |
PCI_TYPE0_SERREN |
PCI_TYPE_IDSEL_STEPPING |
PCI_TYPE0_PARITY_ERR_EN |
PCI_TYPE_VGA_PALETTE_SNOOP |
PCI_TYPE_MWI_ENABLE |
PCI_TYPE0_SPECIAL_CYCLE_OPERATION |
PCI_TYPE0_BUS_MASTER_EN |
PCI_TYPE0_MEM_SPACE_EN |
PCI_TYPE0_IO_EN |
| Access |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RO |
RW/1C/V |
RO |
RO |
RO |
RO |
RO/V |
RO |
- |
RO |
RW |
RO |
RW |
RO |
RW |
RO |
RO |
RO |
RW |
RW/V |
RO/V |
[31:31] RW/1C/V |
DETECTED_PARITY_ERR
Detected Parity Error.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register. |
|
[30:30] RW/1C/V |
SIGNALED_SYS_ERR
Signaled System Error.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL message, and the SERR# Enable bit in the Command register is 1b. For Functions that do not send ERR_FATAL or ERR_NONFATAL messages, the controller hardwires this bit to 0b. |
|
[29:29] RW/1C/V |
RCVD_MASTER_ABORT
Received Master Abort.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit is set when a Requester receives a Completion with Unsupported Request Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b. |
|
[28:28] RW/1C/V |
RCVD_TARGET_ABORT
Received Target Abort.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit is set when a Requester receives a Completion with Completer Abort Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b. |
|
[27:27] RW/1C/V |
SIGNALED_TARGET_ABORT
Signaled Target Abort.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. The controller hardwires this bit to 0b for Functions that do not signal Completer Abort. |
|
[26:25] RO |
DEV_SEL_TIMING
DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this field to 00b.
Reset: hex:0x0;
|
[24:24] RW/1C/V |
MASTER_DPE
Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Function receives a Poisoned Completion - Function transmits a Poisoned Request If the Parity Error Response bit is 0b, this bit is never set.
Reset: hex:0x0;
|
[23:23] RO |
FAST_B2B_CAP
Fast Back to Back Transaction Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[22:22] RO |
RSVDP_22
Reserved for future use.
Reset: hex:0x0;
|
[21:21] RO |
FAST_66MHZ_CAP
66MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[20:20] RO |
CAP_LIST
Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.
Reset: hex:0x1;
|
[19:19] RO/V |
INT_STATUS
Emulation interrupt pending. When set, indicates that an INTx emulation interrupt is pending internally in the Function. Setting the Interrupt Disable bit has no effect on the state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[18:17] RO |
RSVDP_17
Reserved for future use.
Reset: hex:0x0;
|
[15:11] RO |
PCI_TYPE_RESERV
Reserved.
Reset: hex:0x00;
|
[10:10] RW |
PCI_TYPE0_INT_EN
Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts.
When set, Functions are prevented from asserting INTx interrupts.
Note:
Any INTx emulation interrupts already asserted by the Function must be de-asserted when this bit is Set. INTx interrupts use virtual wires that must, if asserted, be de-asserted using the appropriate Deassert_INTx message(s) when this bit is set.
Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected.
For functions that generate INTx interrupts, this bit is required. For functions that do not generate INTx interrupts, this bit is optional.
Reset: hex:0x0;
|
[09:09] RO |
RSVDP_9
Reserved for future use.
Reset: hex:0x0;
|
[08:08] RW |
PCI_TYPE0_SERREN
SERR# Enable. When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.
Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control register.
Reset: hex:0x0;
|
[07:07] RO |
PCI_TYPE_IDSEL_STEPPING
IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[06:06] RW |
PCI_TYPE0_PARITY_ERR_EN
Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register.
Reset: hex:0x0;
|
[05:05] RO |
PCI_TYPE_VGA_PALETTE_SNOOP
VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge architecture specification. Its functionality does not apply to PCI Express, the controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[04:04] RO |
PCI_TYPE_MWI_ENABLE
Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge architecture specification. Its functionality does not apply to PCI Express, the controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[03:03] RO |
PCI_TYPE0_SPECIAL_CYCLE_OPERATION
Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[02:02] RW |
PCI_TYPE0_BUS_MASTER_EN
Bus Master Enable. Controls the ability of a Function to issue Memory and I/O Read/Write requests. - When this bit is set, the Function is allowed to issue Memory or I/O Requests. - When this bit is clear, the Function is not allowed to issue any Memory or I/O Requests. Requests other than Memory or I/O Requests are not controlled by this bit.
Note: MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[01:01] RW/V |
PCI_TYPE0_MEM_SPACE_EN
Memory Space Enable. Controls a Function's response to Memory Space accesses. - When this bit is set, the Function is enabled to decode the address and further process Memory Space accesses. - When this bit is clear, all received Memory Space accesses are caused to be handled as Unsupported Requests. For a Function does not support Memory Space accesses, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: !has_mem_bar ? RO : RW - Dbi: !has_mem_bar ? RO : RW
Reset: hex:0x0;
|
[00:00] RO/V |
PCI_TYPE0_IO_EN
IO Space Enable. Controls a Function's response to I/O Space accesses. - When this bit is set, the Function is enabled to decode the address and further process I/O Space accesses. - When this bit is clear, all received I/O accesses are caused to be handled as Unsupported Requests. For a Function that does not support I/O Space accesses, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: !has_io_bar ? RO : RW - Dbi: !has_io_bar ? RO : RW
Reset: hex:0x0;
|
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+0x00000008 Register(32 bit) CLASS_CODE_REVISION_ID
Class Code and Revision ID Register.
This register specifies the class code and revision ID of a function.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000008 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x02800001 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
| Name |
BASE_CLASS_CODE |
SUBCLASS_CODE |
PROGRAM_INTERFACE |
REVISION_ID |
| Access |
RO |
RO |
RO |
RO |
[31:24] RO |
BASE_CLASS_CODE
Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class, are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x02;
|
[23:16] RO |
SUBCLASS_CODE
Sub-Class Code. Specifies a base class sub-class, which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x80;
|
[15:08] RO |
PROGRAM_INTERFACE
Programming Interface. This field identifies a specific register-level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO |
REVISION_ID
Revision ID. The value in this register specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x01;
|
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+0x0000000c Register(32 bit) BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG
BIST, Header Type, Latency Timer, and Cache Line Size Register.
This register provides the status and controls BIST. It also holds information regarding the header layout, latency timer, and cache line size.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100000c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
BIST |
MULTI_FUNC |
HEADER_TYPE |
LATENCY_MASTER_TIMER |
CACHE_LINE_SIZE |
| Access |
RO |
RO |
RO |
RO |
RW |
[31:24] RO |
BIST
BIST. This register is used for control and status of BIST. For Functions that do not support BIST the controller hardwires the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]: BIST Capable. When Set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST. If BIST Capable is Set, Set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been Set. Writing this bit to 0b has no effect. This bit must be hardwired to 0b if BIST Capable is Clear. - [29:28]: Reserved. - [27:24]: Completion Code. This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is Set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| Max_field_value |
0x0ff |
Max value |
| Min_field_value |
0x0 |
Zero value |
|
[23:23] RO |
MULTI_FUNC
Multi-Function Device. Except where stated otherwise, it is recommended that this bit be set if there are multiple Functions, and clear if there is only one Function.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
Software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure. |
| SET |
0x1 |
Indicates that the Device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0 |
|
[22:16] RO |
HEADER_TYPE
Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0000b encoding.
Reset: hex:0x00;
|
[15:08] RO |
LATENCY_MASTER_TIMER
Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.
Reset: hex:0x00;
|
[07:00] RW |
CACHE_LINE_SIZE
Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express device behavior.
Reset: hex:0x00;
|
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+0x00000010 Register(32 bit) BAR0_REG
BAR0 Register.
System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000010 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000004 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
| Name |
BAR0_START |
BAR0_PREFETCH |
BAR0_TYPE |
BAR0_MEM_IO |
| Access |
RW/V |
RO/V |
RO/V |
RO/V |
[31:04] RW/V |
BAR0_START
- BAR0_START. BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base Address.
Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0000000;
|
[03:03] RO/V |
BAR0_PREFETCH
- BAR0 Prefetchable.
Memory Space: Set to one if data is prefetchable.
A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.
IO Space: Not applicable.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[02:01] RO/V |
BAR0_TYPE
- BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| BAR_32 |
0x0 |
Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. |
| BAR_64 |
0x2 |
Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. |
| RSVD_1 |
0x1 |
Reserved. |
| RSVD_2 |
0x3 |
Reserved. |
|
[00:00] RO/V |
BAR0_MEM_IO
- BAR0 Memory Space Indicator. - This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. - Base Address registers that map to I/O Space must return a 1b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x00000014 Register(32 bit) BAR1_REG
BAR1 Register.
System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000014 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
BAR1_START |
BAR1_PREFETCH |
BAR1_TYPE |
BAR1_MEM_IO |
| Access |
RW/V |
RW/V |
RW/V |
RW/V |
[31:04] RW/V |
BAR1_START
- BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base Address.
Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0000000;
|
[03:03] RW/V |
BAR1_PREFETCH
- BAR1 Prefetchable.
Memory Space: Set to one if data is prefetchable.
A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.
IO Space: Not applicable.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[02:01] RW/V |
BAR1_TYPE
- BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR_32 |
0x0 |
Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. |
| BAR_64 |
0x2 |
Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. |
| RSVD_1 |
0x1 |
Reserved. |
| RSVD_2 |
0x3 |
Reserved. |
|
[00:00] RW/V |
BAR1_MEM_IO
- BAR1 Memory Space Indicator. - This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. - Base Address registers that map to I/O Space must return a 1b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
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+0x00000018 Register(32 bit) BAR2_REG
BAR2 Register.
System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000018 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000004 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
| Name |
BAR2_START |
BAR2_PREFETCH |
BAR2_TYPE |
BAR2_MEM_IO |
| Access |
RW/V |
RO/V |
RO/V |
RO/V |
[31:04] RW/V |
BAR2_START
BAR2 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address.
Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0000000;
|
[03:03] RO/V |
BAR2_PREFETCH
BAR2 Prefetchable. - Memory Space: Set to one if data is prefetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicable
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[02:01] RO/V |
BAR2_TYPE
BAR2 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| BAR_32 |
0x0 |
Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. |
| BAR_64 |
0x2 |
Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. |
| RSVD_1 |
0x1 |
Reserved. |
| RSVD_2 |
0x3 |
Reserved. |
|
[00:00] RO/V |
BAR2_MEM_IO
BAR2 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
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+0x0000001c Register(32 bit) BAR3_REG
BAR3 Register.
System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100001c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
BAR3_START |
BAR3_PREFETCH |
BAR3_TYPE |
BAR3_MEM_IO |
| Access |
RW/V |
RW/V |
RW/V |
RW/V |
[31:04] RW/V |
BAR3_START
BAR3 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address.
Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0000000;
|
[03:03] RW/V |
BAR3_PREFETCH
BAR3 Prefetchable. - Memory Space: Set to one if data is prefetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicable
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[02:01] RW/V |
BAR3_TYPE
BAR3 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR_32 |
0x0 |
Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. |
| BAR_64 |
0x2 |
Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. |
| RSVD_1 |
0x1 |
Reserved. |
| RSVD_2 |
0x3 |
Reserved. |
|
[00:00] RW/V |
BAR3_MEM_IO
BAR3 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
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+0x00000020 Register(32 bit) BAR4_REG
BAR4 Register.
System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000020 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
BAR4_START |
BAR4_PREFETCH |
BAR4_TYPE |
BAR4_MEM_IO |
| Access |
RW/V |
RO/V |
RO/V |
RO/V |
[31:04] RW/V |
BAR4_START
BAR4 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address.
Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0000000;
|
[03:03] RO/V |
BAR4_PREFETCH
BAR4 Prefetchable. - Memory Space: Set to one if data is prefetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicable
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[02:01] RO/V |
BAR4_TYPE
BAR4 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR_32 |
0x0 |
Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. |
| BAR_64 |
0x2 |
Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. |
| RSVD_1 |
0x1 |
Reserved. |
| RSVD_2 |
0x3 |
Reserved. |
|
[00:00] RO/V |
BAR4_MEM_IO
BAR4 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
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+0x00000024 Register(32 bit) BAR5_REG
BAR5 Register.
System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000024 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
BAR5_START |
BAR5_PREFETCH |
BAR5_TYPE |
BAR5_MEM_IO |
| Access |
RW/V |
RO/V |
RO/V |
RO/V |
[31:04] RW/V |
BAR5_START
BAR5 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address.
Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0000000;
|
[03:03] RO/V |
BAR5_PREFETCH
BAR5 Prefetchable. - Memory Space: Set to one if data is prefetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicable
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[02:01] RO/V |
BAR5_TYPE
BAR5 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR_32 |
0x0 |
Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. |
| BAR_64 |
0x2 |
Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. |
| RSVD_1 |
0x1 |
Reserved. |
| RSVD_2 |
0x3 |
Reserved. |
|
[00:00] RO/V |
BAR5_MEM_IO
BAR5 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
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+0x00000028 Register(32 bit) CARDBUS_CIS_PTR_REG
CardBus CIS Pointer Register.
This register holds the CardBus CIS pointer.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000028 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CARDBUS_CIS_POINTER |
| Access |
RO |
[31:00] RO |
CARDBUS_CIS_POINTER
CardBus CIS Pointer. Its functionality does not apply to PCI Express. It must be hardwired to 0000 0000h.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x00000000;
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+0x0000002c Register(32 bit) SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG
Subsystem ID and Subsystem Vendor ID Register.
These registers are used to uniquely identify the add-in card or subsystem where the PCI Express component resides. They provide a mechanism for vendors to distinguish their products from one another even though the assemblies may have the same PCI Express component on them (and, therefore, the same Vendor ID and Device ID).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100002c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0dd68086 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
| Name |
SUBSYS_DEV_ID |
SUBSYS_VENDOR_ID |
| Access |
RO |
RO |
[31:16] RO |
SUBSYS_DEV_ID
Subsystem ID.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0dd6;
|
[15:00] RO |
SUBSYS_VENDOR_ID
Subsystem Vendor ID. Subsystem Vendor IDs can be obtained from the PCI SIG and are used to identify the vendor of the add-in card or subsystem. Values for the Subsystem ID are vendor-specific.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x8086;
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+0x00000030 Register(32 bit) EXP_ROM_BASE_ADDR_REG
Expansion ROM BAR Register.
This register handles the base address and size information for this expansion ROM.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000030 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EXP_ROM_BASE_ADDRESS |
RSVDP_8 |
ROM_BAR_VALIDATION_DETAILS |
ROM_BAR_VALIDATION_STATUS |
ROM_BAR_ENABLE |
| Access |
RW/V |
RO |
RW/V |
RW/V |
RW/V |
[31:11] RW/V |
EXP_ROM_BASE_ADDRESS
Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires.
Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R
Reset: hex:0x000000;
|
[10:08] RO |
RSVDP_8
Reserved for future use.
Reset: hex:0x0;
|
[07:04] RW/V |
ROM_BAR_VALIDATION_DETAILS
Expansion ROM Validation Details. The field contains optional, implementation-specific details associated with Expansion ROM Validation. - If validation is in progress (Expansion ROM Validation Status is 001b), non-zero values of this field represent implementation-specific indications of the phase of the validation progress (for example, 50% complete). The value 0000b indicates that no validation progress information is provided. - If validation is completed (Expansion ROM Validation Status 010b to 111b inclusive), non-zero values in this field represent additional implementation-specific information. The value 0000b indicates that no information is provided. - When validation is supported and this field is not implemented, this field must be hardwired to 0000b.
Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1 && DBI_RO_WR_EN == 1 ) then R/W else R Note: This register field is sticky.
Reset: hex:0x0;
|
[03:01] RW/V |
ROM_BAR_VALIDATION_STATUS
Expansion ROM Validation Status. When this field is non-zero, it indicates the status of hardware validation of the Expansion ROM contents. - If the Function does not support validation, this field must be hardwired to 000b. - It is optional whether an implementation is capable of returning Validation Status values 011b, 101b, 110b, or 111b.
Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1 && DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FIVE |
0x5 |
Validation Fail Valid but untrusted contents (For example, Out of Date, Expired or Revoked Certificate). |
| FOUR |
0x4 |
Validation Fail Invalid contents. |
| ONE |
0x1 |
Validation in Progress. |
| SEVEN |
0x7 |
Warning Pass Validation Passed with implementation-specific warning. Valid and trusted contents. |
| SIX |
0x6 |
Warning Pass Validation Passed with implementation-specific warning. Valid contents, trust test was not performed. |
| THREE |
0x3 |
Validation Pass Valid and trusted contents. |
| TWO |
0x2 |
Validation Pass Valid contents, trust test was not performed. |
| ZERO |
0x0 |
Validation not supported. |
|
[00:00] RW/V |
ROM_BAR_ENABLE
Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.
Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register. |
| ZERO |
0x0 |
When this bit is 0b, the Function's expansion ROM address space is disabled. |
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+0x00000034 Register(32 bit) PCI_CAP_PTR_REG
Capabilities Pointer Register.
This register is used to point to a linked list of capabilities implemented by a Function.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000034 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000040 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_8 |
CAP_POINTER |
| Access |
RO |
RO |
[31:08] RO |
RSVDP_8
Reserved for future use.
Reset: hex:0x000000;
|
[07:00] RO |
CAP_POINTER
Capabilities Pointer. This register points to a valid capability structure. Either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are reserved, the controller sets it to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x40;
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+0x0000003c Register(32 bit) MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG
Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register.
The Interrupt Line register communicates interrupt line routing information. The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100003c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x000001ff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
RSVDP_16 |
INT_PIN |
INT_LINE |
| Access |
RO |
RO |
RW |
[31:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0000;
|
[15:08] RO |
INT_PIN
Interrupt Pin. The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses. All encodings other than the defined encodings are reserved. PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.
Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth. For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x01;
| Valid Values |
| Name | Value(s) | Description |
| INTA |
0x1 |
Map to legacy interrupt Messages for INTA |
| INTB |
0x2 |
Map to legacy interrupt Messages for INTB |
| INTC |
0x3 |
Map to legacy interrupt Messages for INTC |
| INTD |
0x4 |
Map to legacy interrupt Messages for INTD |
| NO_INT |
0x0 |
Indicates that the Function uses no legacy interrupt Message(s). |
|
[07:00] RW |
INT_LINE
Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.
Reset: hex:0xff;
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+0x00000040 Register(32 bit) CAP_ID_NXT_PTR_REG
Power Management Capabilities Register.
This register provides information refarding the Power Management Capabilities.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000040 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0xdfc35001 |
|
|
Unaffected |
0xf8100000 |
|
|
Undefined |
0x00100000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
- |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
| Name |
PME_SUPPORT |
D2_SUPPORT |
D1_SUPPORT |
AUX_CURR |
DSI |
- |
PME_CLK |
PM_SPEC_VER |
PM_NEXT_POINTER |
PM_CAP_ID |
| Access |
RO/V |
RO |
RO |
RO |
RO |
- |
RO |
RO |
RO |
RO |
[31:27] RO/V |
PME_SUPPORT
PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. - bit(27) X XXX1b - PME can be generated from D0 - bit(28) X XX1Xb - PME can be generated from D1 - bit(29) X X1XXb - PME can be generated from D2 - bit(30) X 1XXXb - PME can be generated from D3hot - bit(31) 1 XXXXb - PME can be generated from D3cold Bit 31 (PME can be asserted from D3cold) represents a special case. Functions that set this bit require some sort of auxiliary power source. Implementation specific mechanisms are recommended to validate that the power source is available before setting this bit.
Each bit that corresponds to a supported D-state must be set for PCI-PCI Bridge structures representing Ports on Root Complexes/Switches to indicate that the Bridge will forward PME Messages. Bit 31 must only be set if the Port is still able to forward PME Messages when main power is not available.
The read value from this field is the write value && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are fields in this register.
The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1b;
|
[26:26] RO |
D2_SUPPORT
D2_Support. If this bit is set, this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
|
[25:25] RO |
D1_SUPPORT
D1_Support. If this bit is set, this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
|
[24:22] RO |
AUX_CURR
Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function.
If this function implements the Power Management Data Register, the controller hardwires this field to 000b.
If PME_Support is 0 xxxxb (PME assertion from D3cold is not supported) and the Aux Power PM Enable feature is not implemented, the controller hardwires this field to 000b.
For functions where PME_Support is 1 xxxxb (PME assertion from D3cold is supported), and which do not implement the Power Management Data Register, the encodings defined in Values: apply: For encoding 000b, when the add-in card is self powered (e.g., it contains a battery), it is recommended that the Power Budgeting Extended Capability be used to report the thermal requirements of the add-in card. Note: Additional Aux power is permitted to be allocated using the firmware based mechanism (see the Request D3 Cold Aux Power Limit _DSM call as defined in [Firmware]). Additional Aux power is also permitted to be allocated by selecting a PM Sub State in the Power Limit mechanism (see Section 7.8.1.3)
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x7;
| Valid Values |
| Name | Value(s) | Description |
| SELF_ |
0x0 |
0 mW (no Vaux power or self powered) |
| _055mA_ |
0x1 |
182 mW (e.g., 3.3 V at 55 mA) |
| _100mA_ |
0x2 |
330 mW (e.g., 3.3 V at 100 mA) |
| _160mA_ |
0x3 |
528 mW (e.g., 3.3 V at 160 mA) |
| _220mA_ |
0x4 |
726 mW (e.g., 3.3 V at 220 mA) |
| _270mA_ |
0x5 |
891 mW (e.g., 3.3 V at 270 mA) |
| _320mA_ |
0x6 |
1056 mW (e.g., 3.3 V at 320 mA) |
| _375mA_ |
0x7 |
1238 mW (e.g., 3.3 V at 375 mA) |
|
[21:21] RO |
DSI
Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required.
When set, indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized state.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x0;
|
[19:19] RO |
PME_CLK
PME Clock. Does not apply to PCI Express, the controller hardwires it to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[18:16] RO |
PM_SPEC_VER
Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0>.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x3;
|
[15:08] RO |
PM_NEXT_POINTER
Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list, this field is set to 00h.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x50;
|
[07:00] RO |
PM_CAP_ID
Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h.
Reset: hex:0x01;
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+0x00000044 Register(32 bit) CON_STATUS_REG
Power Management Control and Status Register.
This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000044 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000008 |
|
|
Unaffected |
0x00000103 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
| Name |
DATA_REG_ADD_INFO |
BUS_PWR_CLK_CON_EN |
B2_B3_SUPPORT |
RSVDP_16 |
PME_STATUS |
DATA_SCALE |
DATA_SELECT |
PME_ENABLE |
RSVDP_4 |
NO_SOFT_RST |
RSVDP_2 |
POWER_STATE |
| Access |
RO |
RO |
RO |
RO |
RW/1C/V |
RO |
RO |
RW/V |
RO |
RO |
RO |
RW/V |
[31:24] RO |
DATA_REG_ADD_INFO
Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field.
Reset: hex:0x00;
|
[23:23] RO |
BUS_PWR_CLK_CON_EN
Bus Power/Clock Control Enable. If this field is set, Bus Power/Clock Control is Enable.
Reset: hex:0x0;
|
[22:22] RO |
B2_B3_SUPPORT
B2B3 Support for D3hot. If this field is set, B2B3 support for D3hot is available.
Reset: hex:0x0;
|
[21:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x00;
|
[15:15] RW/1C/V |
PME_STATUS
PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear, this bit is permitted to be hardwired to 0b. Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this register value is not modified by Conventional Reset or FLR.
Note: This register field is sticky.
Reset: hex:0x0;
|
[14:13] RO |
DATA_SCALE
Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. This field is a required component of the Power Management Data Register (offset 7) and must be implemented if the Power Management Data Register is implemented. If the Power Management Data Registeris not implemented, this field must be hardwired to zero.
For more information, see 7.5.2.3 section of PCI Express Base Specification.
Reset: hex:0x0;
|
[12:09] RO |
DATA_SELECT
Data_Select. This 4-bit field is used to select which data is to be reported through the Power Management Data Register and Data_Scale field. If the Power Management Data field is not implemented, this field must be hardwired to zero. The default of this field is zero.
Reset: hex:0x0;
|
[08:08] RW/V |
PME_ENABLE
PME_En. - When set, the function is permitted to generate a PME. - When clear, the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is available this bit is RWS and the bit is not modified by Conventional Reset or FLR.
If PME_Support is 0 xxxxb, this field is not sticky (RW) and defaults to 0b in response to a Conventional Reset or an FLR.
If PME_Support is 0 0000b, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[07:04] RO |
RSVDP_4
Reserved for future use.
Reset: hex:0x0;
|
[03:03] RO |
NO_SOFT_RST
No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. This bit MUST @FLIT be Set. - When set, this transition preserves internal function state. The function is in D0Active and no additional software intervention is required. - When clear, this transition results in undefined internal function state. Regardless of this bit, functions that transition from D3hot to D0 by Fundamental Reset must return to D0Uninitialized with only PME context preserved if PME is supported and enabled.
If a VF implements the Power Management Capability, the VF's value of this field must be identical to the associated PF's value.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
|
[02:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x0;
|
[01:00] RW/V |
POWER_STATE
PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. You can write to this register; however, the read-back value is the actual power state, not the write value. If you attempt to write an unsupported, optional state to this field, the write operation completes normally; however, the data is discarded and no state change occurs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| D0 |
0x0 |
D0 power state |
| D1 |
0x1 |
D1 power state |
| D2 |
0x2 |
D2 power state |
| D3hot |
0x3 |
D3hot D3hot power state |
|
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+0x00000050 Register(32 bit) PCI_MSI_CAP_ID_NEXT_CTRL_REG
MSI Capability Header and Message Control Register.
This register holds MSI Capability Header information and controls the MSI behaviour.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000050 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x01887005 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
| Name |
RSVDP_27 |
PCI_MSI_EXT_DATA_EN |
PCI_MSI_EXT_DATA_CAP |
PCI_PVM_SUPPORT |
PCI_MSI_64_BIT_ADDR_CAP |
PCI_MSI_MULTIPLE_MSG_EN |
PCI_MSI_MULTIPLE_MSG_CAP |
PCI_MSI_ENABLE |
PCI_MSI_CAP_NEXT_OFFSET |
PCI_MSI_CAP_ID |
| Access |
RO |
RW |
RO |
RO |
RO |
RW |
RO |
RW |
RO |
RO |
[31:27] RO |
RSVDP_27
Reserved for future use.
Reset: hex:0x00;
|
[26:26] RW |
PCI_MSI_EXT_DATA_EN
Extended Message Data Enable. - If set, the function is enabled to provide Extended Message Data. - If clear, the function is not enabled to provide Extended Message Data.
Note: The access attributes of this field are as follows: - Wire: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO
Reset: hex:0x0;
|
[25:25] RO |
PCI_MSI_EXT_DATA_CAP
Extended Message Data Capable. - If set, the function is capable of providing Extended Message Data. - If clear, the function does not support providing Extended Message Data.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x0;
|
[24:24] RO |
PCI_PVM_SUPPORT
Per-Vector Masking Capable. - If set, the function supports MSI Per-Vector Masking. - If clear, the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device.
Reset: hex:0x1;
|
[23:23] RO |
PCI_MSI_64_BIT_ADDR_CAP
64-bit Address Capable. This bit must be set if the function is a PCI Express Endpoint,as indicated by the value in the Device/Port Type field
This bit MUST@FLIT be Set
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| set_0 |
0x0 |
If set, the function is capable of sending a 64-bit message address. |
| set_1 |
0x1 |
If clear, the function is not capable of sending a 64-bit message address. |
|
[22:20] RW |
PCI_MSI_MULTIPLE_MSG_EN
Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a function requests four vectors (indicated by a Multiple Message Capable encoding of 010b), system software can allocate either four, two, or one vector by writing a 010b, 001b, or 000b to this field, respectively. When MSI is enabled, a function will be allocated at least 1 vector. All encodings other than the defined encodings are reserved.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _16_VECTOR |
0x4 |
16 vectors allocated |
| _1_VECTOR |
0x0 |
1 vector allocated |
| _2_VECTOR |
0x1 |
2 vectors allocated |
| _32_VECTOR |
0x5 |
32 vectors allocated |
| _4_VECTOR |
0x2 |
4 vectors allocated |
| _8_VECTOR |
0x3 |
8 vectors allocated |
|
[19:17] RO |
PCI_MSI_MULTIPLE_MSG_CAP
Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors, it requests four by initializing this field to 010b). All encodings other than the defined encodings are reserved.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x4;
| Valid Values |
| Name | Value(s) | Description |
| _16_VECTOR |
0x4 |
16 vectors requested |
| _1_VECTOR |
0x0 |
1 vector requested |
| _2_VECTOR |
0x1 |
2 vectors requested |
| _32_VECTOR |
0x5 |
32 vectors requested |
| _4_VECTOR |
0x2 |
4 vectors requested |
| _8_VECTOR |
0x3 |
8 vectors requested |
|
[16:16] RW |
PCI_MSI_ENABLE
MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear, the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function's service request. For more information on control of INTx interrupts, see section 7.5.1.1 of PCI Express Base Specification. - If clear, the function is prohibited from using MSI to request service.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[15:08] RO |
PCI_MSI_CAP_NEXT_OFFSET
Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x70;
|
[07:00] RO |
PCI_MSI_CAP_ID
Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure.
Reset: hex:0x05;
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+0x00000054 Register(32 bit) MSI_CAP_OFF_04H_REG
Message Address Register for MSI (Offset 04h).
This register holds the system specified message address for an MSI transaction.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000054 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PCI_MSI_CAP_OFF_04H |
RSVDP_0 |
| Access |
RW |
RO |
[31:02] RW |
PCI_MSI_CAP_OFF_04H
Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set, the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI transaction. Address[1:0] are set to 00b.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
|
[01:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x0;
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+0x00000058 Register(32 bit) MSI_CAP_OFF_08H_REG
Message Address Register for MSI (Offset 08h).
For a function that supports a 32-bit message address,
- bits[31:16] of this register represent the Extended Message Data, and
- bits[15:0] of this register represent the Message Data
For a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000058 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PCI_MSI_CAP_OFF_0AH |
PCI_MSI_CAP_OFF_08H |
| Access |
RW |
RW |
[31:16] RW |
PCI_MSI_CAP_OFF_0AH
For a function that supports a 32-bit message address, this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is outside the MSI Capability structure and undefined. For the MSI Capability structures with Per-vector Masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is RsvdP. If the Extended Message Data Enable bit (bit 26 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the DWORD Memory Write transaction uses Extended Message Data for the upper 16 bits; otherwise, it uses 0000h for the upper 16 bits.
For a function that supports a 64-bit message address, it contains upper 16 bits of the Message Upper Address.
Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R
Reset: hex:0x0000;
|
[15:00] RW |
PCI_MSI_CAP_OFF_08H
For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.
For a function that supports a 64-bit message address, it contains lower 16 bits of the Message Upper Address.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0000;
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+0x0000005c Register(32 bit) MSI_CAP_OFF_0CH_REG
Message Address Register for MSI (Offset 0Ch).
For a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.
For a function that supports a 64-bit message address, this register contains Message Data.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100005c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PCI_MSI_CAP_OFF_0EH |
PCI_MSI_CAP_OFF_0CH |
| Access |
RW |
RW |
[31:16] RW |
PCI_MSI_CAP_OFF_0EH
For a function that supports a 32-bit message address, this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.
For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data).
Note: The access attributes of this field are as follows: - Wire: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO
Reset: hex:0x0000;
|
[15:00] RW |
PCI_MSI_CAP_OFF_0CH
For a function that supports a 32-bit message address, this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.
For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.
Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R
Reset: hex:0x0000;
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+0x00000060 Register(32 bit) MSI_CAP_OFF_10H_REG
Message Address Register for MSI (Offset 10h).
For a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.
For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000060 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PCI_MSI_CAP_OFF_10H |
| Access |
RW |
[31:00] RW |
PCI_MSI_CAP_OFF_10H
Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit, contains Mask Bits.
Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R
Reset: hex:0x00000000;
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+0x00000064 Register(32 bit) MSI_CAP_OFF_14H_REG
Message Address Register for MSI (Offset 14h).
Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000064 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PCI_MSI_CAP_OFF_14H |
| Access |
RO |
[31:00] RO |
PCI_MSI_CAP_OFF_14H
Pending Bits. For each pending bit that is set, the function has a pending associated message.
Reset: hex:0x00000000;
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+0x00000070 Register(32 bit) PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG
PCI Express Capabilities, ID, Next Pointer Register.
This is the PCI Express Capabilities, ID, and Next Pointer Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000070 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x0002b010 |
|
|
Unaffected |
0x80f00000 |
|
|
Undefined |
0x80000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| Name |
- |
RSVD |
PCIE_INT_MSG_NUM |
PCIE_SLOT_IMP |
PCIE_DEV_PORT_TYPE |
PCIE_CAP_REG |
PCIE_CAP_NEXT_PTR |
PCIE_CAP_ID |
| Access |
- |
RO |
RO |
RO |
RO/V |
RO |
RO |
RO |
[30:30] RO |
RSVD
Reserved.
Reset: hex:0x0;
|
[29:25] RO |
PCIE_INT_MSG_NUM
PCIE Interrupt Message Number. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this Capability structure.
For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register.
For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant.
If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x00;
|
[24:24] RO |
PCIE_SLOT_IMP
Slot Implemented. When set, this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit is undefined for Upstream Ports.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
Reset: hex:0x0;
|
[23:20] RO/V |
PCIE_DEV_PORT_TYPE
Device/Port Type. Indicates the specific type of this PCI Express function.
Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI Configuration Space header are: Defined encodings for functions that implement a Type 01h PCI Configuration Space header are: All other encodings are Reserved.
Note: Different Endpoint types have notably different requirements in Section 1.3.2 of PCI Express Base Specification regarding I/O resources, Extended Configuration Space, and other capabilities.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DSP_PCIE_SWITCH |
0x6 |
Downstream Port of PCI Express Switch |
| PCIE_EP |
0x0 |
PCI Express Endpoint |
| PCIE_LEGACY_EP |
0x1 |
Legacy PCI Express Endpoint |
| ROOT_PORT_PCIE_RC |
0x4 |
Root Port of PCI Express Root Complex |
| USP_PCIE_SWITCH |
0x5 |
Upstream Port of PCI Express Switch |
|
[19:16] RO |
PCIE_CAP_REG
Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example, through a new Capability field) is permitted to increment this field. All such changes to the PCI Express Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as functions reporting any such Capability Version numbers will contain a PCI Express Capability structure that is compatible with that piece of software. The controller hardwires this field to 2h for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.
Note: This register field is sticky.
Reset: hex:0x2;
|
[15:08] RO |
PCIE_CAP_NEXT_PTR
Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0xb0;
|
[07:00] RO |
PCIE_CAP_ID
Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure.
Reset: hex:0x10;
|
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+0x00000074 Register(32 bit) DEVICE_CAPABILITIES_REG
Device Capabilities Register.
The Device Capabilities register identifies PCI Express device function specific capabilities.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000074 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00008fe1 |
|
|
Unaffected |
0x2ffe0000 |
|
|
Undefined |
0x20020000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
| Name |
RSVDP_31 |
PCIE_CAP_TEE_IO_SUPPORTED |
- |
PCIE_CAP_FLR_CAP |
PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE |
PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE |
- |
RSVDP_16 |
PCIE_CAP_ROLE_BASED_ERR_REPORT |
RSVDP_12 |
PCIE_CAP_EP_L1_ACCPT_LATENCY |
PCIE_CAP_EP_L0S_ACCPT_LATENCY |
PCIE_CAP_EXT_TAG_SUPP |
PCIE_CAP_PHANTOM_FUNC_SUPPORT |
PCIE_CAP_MAX_PAYLOAD_SIZE |
| Access |
RO |
RO |
- |
RO |
RO/V |
RO/V |
- |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:30] RO |
PCIE_CAP_TEE_IO_SUPPORTED
Indicates that the Function implements the TEE-IO functionality as described by the TEE Device Interface Security Protocol (TDISP). Function0 represents the whole port capabilitiy and all other Functions should be set to the same value as Function0.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
Clear. |
| SET |
0x1 |
Set. |
|
[28:28] RO |
PCIE_CAP_FLR_CAP
Function Level Reset Capability This field applies to Endpoints only. For all other Function types the controller hardwires this field to 0b. For PFs and VFs, the feature is mandatory and this field must be set. For more information on Function Level Reset mechanism, see section 6.6.2 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates the Function supports the optional Function Level Reset mechanism. |
| CLEAR |
0x0 |
Clear |
|
[27:26] RO/V |
PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE
Captured Slot Power Limit Scale Applicable to Upstream Ports only. Specifies the scale used for the SET_SLOT_PWR_LIMIT_VAL parameter. This value is set by the Set_Slot_Power_Limit Message or hardwired to 00b. For VFs, the field value when read is undefined. For more information, see section 6.9 of the PCI Express Base Specification.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _0_001X |
0x3 |
0.001x |
| _0_01X |
0x2 |
0.01x |
| _0_1X |
0x1 |
0.1x |
| _1_0X |
0x0 |
1.0x |
|
[25:18] RO/V |
PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE
Captured Slot Power Limit Value Applicable for Upstream Ports only. In combination with the PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE value, specifies the upper limit on power available to the adapter. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE field except when the PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE field equals 00b (1.0x) and the Captured Slot Power Limit Value exceeds 0xEF, then alternative encodings are used. This value is set by the Set_Slot_Power_Limit Message or hardwired to 00h. For VFs, the field value when read is undefined. For more information, see section 6.9 and 7.5.3.9 of the PCI Express Base Specification.
Reset: hex:0x00;
|
[16:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0;
|
[15:15] RO |
PCIE_CAP_ROLE_BASED_ERR_REPORT
Role-Based Error Reporting. When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
|
[14:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x0;
|
[11:09] RO |
PCIE_CAP_EP_L1_ACCPT_LATENCY
Endpoint L1 Acceptable Latency. This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the Endpoint's internal buffering. Power management software uses the reported L1 Acceptable Latency number to compare against the L1 Exit Latencies reported (see below) by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L1 entry can be used with no loss of performance. For functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.
Reset: hex:0x7;
| Valid Values |
| Name | Value(s) | Description |
| MAX_16US |
0x4 |
Maximum of 16 us |
| MAX_1US |
0x0 |
Maximum of 1 us |
| MAX_2US |
0x1 |
Maximum of 2 us |
| MAX_32US |
0x5 |
Maximum of 32 us |
| MAX_4US |
0x2 |
Maximum of 4 us |
| MAX_64US |
0x6 |
Maximum of 64 us |
| MAX_8US |
0x3 |
Maximum of 8 us |
| NO_LIMIT |
0x7 |
No limit |
|
[08:06] RO |
PCIE_CAP_EP_L0S_ACCPT_LATENCY
Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. It is essentially an indirect measure of the Endpoint's internal buffering.
Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L0s entry can be used with no loss of performance. For functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x7;
| Valid Values |
| Name | Value(s) | Description |
| MAX_128NS |
0x1 |
Maximum of 128 ns |
| MAX_1US |
0x4 |
Maximum of 1 us |
| MAX_256NS |
0x2 |
Maximum of 256 ns |
| MAX_2US |
0x5 |
Maximum of 2 us |
| MAX_4US |
0x6 |
Maximum of 4 us |
| MAX_512NS |
0x3 |
Maximum of 512 ns |
| MAX_64NS |
0x0 |
Maximum of 64 ns |
| NO_LIMIT |
0x7 |
No limit |
|
[05:05] RO |
PCIE_CAP_EXT_TAG_SUPP
Extended Tag Field Supported
This field, in combination with the PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT field of the DEVICE_CAPABILITIES2_REG register and DEV3_CAP_14B_TAG_REQUEST_SUPP field of the DEVICE_CAPABILITIES3_REG register indicates the maximum supported size of the Tag field as a Requester. This field must be set if the PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT field or the DEV3_CAP_14B_TAG_REQUEST_SUPP is set.
Note: 8-bit Tag field generation must be enabled by the PCIE_CAP_EXT_TAG_EN field in the DEVICE_CONTROL_DEVICE_STATUS register of the Requester Function before 8-bit Tags can be generated by the Requester.
For more information on interactions with enabling the use of 10-Bit or 14-Bit Tags, see section 2.2.6.2 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| _5_TAG |
0x0 |
5-bit Tag Requester Capability supported |
| _8_TAG |
0x1 |
8-bit Tag Requester Capability supported |
|
[04:03] RO |
PCIE_CAP_PHANTOM_FUNC_SUPPORT
Phantom Functions Supported
This field indicates the support for use of unclaimed Function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed Function numbers (called Phantom Functions) with the Tag identifier.
For a PF with its VF Enable bit Set, the use of Phantom Function numbers is not permitted and this field must return 0b when read.
For VFs, this field is not supported and must be hardwired to 0b.
For every Function in an ARI Device, this field must be hardwired to 0b.
The remainder of this field description applies only to non-ARI Multi-Function Devices.
This field indicates the number of most significant bits of the Function Number portion of Requester ID that are logically combined with the Tag identifier.
Note: Phantom Function support for the Function must be enabled by the PCIE_CAP_PHANTOM_FUNC_EN field in the DEVICE_CONTROL_DEVICE_STATUS register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions.
For more information on Tag Extension descriptions, see Section 2.2.6.2 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_1_PHANTOM_PER_FUNC |
0x1 |
The most significant bit of the Function number in Requester ID is used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. |
| MAX_3_PHANTOM_PER_FUNC |
0x2 |
The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as Phantom Functions. |
| NO_PHNATOM_FUNC |
0x0 |
No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent Functions. |
| SINGLE_FUNC_MAX_7_PHANTOM_FUNC |
0x3 |
All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single Function 0 that is permitted to use all other Function Numbers as Phantom Functions. |
|
[02:00] RO |
PCIE_CAP_MAX_PAYLOAD_SIZE
Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. This field MUST @FLIT indicate a minimum of 512 bytes.
If the Rx_MPS_Fixed bit is Set, the Function's Rx_MPS_Limit is fixed with the value indicated by this (Max_Payload_Size Supported) field. Otherwise, the Rx_MPS_Limit is determined by the Max_Payload_Size field (the "MPS setting") in one or more Functions. See section 2.2.2 for important details regarding Multi-Function Devices Defined encodings are: The functions of a Multi-Function Device are permitted to report different values for this field.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MAX_1024B_SIZE |
0x3 |
1024 bytes max payload size |
| MAX_128B_SIZE |
0x0 |
128 bytes max payload size |
| MAX_2048B_SIZE |
0x4 |
2048 bytes max payload size |
| MAX_256B_SIZE |
0x1 |
256 bytes max payload size |
| MAX_4096B_SIZE |
0x5 |
4096 bytes max payload size |
| MAX_512B_SIZE |
0x2 |
512 bytes max payload size |
|
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+0x00000078 Register(32 bit) DEVICE_CONTROL_DEVICE_STATUS
Device Control and Device Status Register.
This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000078 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00102110 |
|
|
Unaffected |
0x00708700 |
|
|
Undefined |
0x00408000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
0 |
1 |
0 |
0 |
0 |
0 |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_23 |
- |
PCIE_CAP_TRANS_PENDING |
PCIE_CAP_AUX_POWER_DETECTED |
PCIE_CAP_UNSUPPORTED_REQ_DETECTED |
PCIE_CAP_FATAL_ERR_DETECTED |
PCIE_CAP_NON_FATAL_ERR_DETECTED |
PCIE_CAP_CORR_ERR_DETECTED |
- |
PCIE_CAP_MAX_READ_REQ_SIZE |
PCIE_CAP_EN_NO_SNOOP |
PCIE_CAP_AUX_POWER_PM_EN |
PCIE_CAP_PHANTOM_FUNC_EN |
PCIE_CAP_EXT_TAG_EN |
PCIE_CAP_MAX_PAYLOAD_SIZE_CS |
PCIE_CAP_EN_REL_ORDER |
PCIE_CAP_UNSUPPORT_REQ_REP_EN |
PCIE_CAP_FATAL_ERR_REPORT_EN |
PCIE_CAP_NON_FATAL_ERR_REPORT_EN |
PCIE_CAP_CORR_ERR_REPORT_EN |
| Access |
RO |
- |
RO/V |
RO/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
- |
RW |
RO |
RW/V |
RO/V |
RW/V |
RW |
RW |
RW |
RW |
RW |
RW |
[31:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x000;
|
[21:21] RO/V |
PCIE_CAP_TRANS_PENDING
Transactions Pending.
Endpoints:
When set, this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.
Root and Switch Ports: The controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[20:20] RO/V |
PCIE_CAP_AUX_POWER_DETECTED
AUX Power Detected Functions that require Aux power report this field as set if Aux power is detected by the Function.
This field is derived by sampling the sys_aux_pwr_det input.
For VFs, this field is not supported and must be hardwired to 0b.
Reset: hex:0x1;
|
[19:19] RW/1C/V |
PCIE_CAP_UNSUPPORTED_REQ_DETECTED
Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function Device, each function indicates status of errors as perceived by the respective function.
Reset: hex:0x0;
|
[18:18] RW/1C/V |
PCIE_CAP_FATAL_ERR_DETECTED
Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.
For Functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.
Reset: hex:0x0;
|
[17:17] RW/1C/V |
PCIE_CAP_NON_FATAL_ERR_DETECTED
Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.
For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.
Reset: hex:0x0;
|
[16:16] RW/1C/V |
PCIE_CAP_CORR_ERR_DETECTED
Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective function.
For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Correctable Error Mask register.
Reset: hex:0x0;
|
[14:12] RW |
PCIE_CAP_MAX_READ_REQ_SIZE
Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. For functions that do not generate Read Requests larger than 128 bytes and functions that do not generate Read Requests on their own behalf, the controller implements this field as Read Only (RO) with a value of 000b.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| MAX_1024B_SIZE |
0x3 |
1024 bytes maximum Read Request size |
| MAX_128B_SIZE |
0x0 |
128 bytes maximum Read Request size |
| MAX_2048B_SIZE |
0x4 |
2048 bytes maximum Read Request size |
| MAX_256B_SIZE |
0x1 |
256 bytes maximum Read Request size |
| MAX_4096B_SIZE |
0x5 |
4096 bytes maximum Read Request size |
| MAX_512B_SIZE |
0x2 |
512 bytes maximum Read Request size |
| RESERVED1 |
0x6 |
RESERVED |
| RESERVED2 |
0x7 |
RESERVED |
|
[11:11] RO |
PCIE_CAP_EN_NO_SNOOP
Enable No Snoop. If this bit is set, the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express Base Specification). Note: Setting this bit to 1b should not cause a function to set the No Snoop attribute on all transactions that it initiates. Even when this bit is set, a function is only permitted to set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system.
The controller hardwires this bit 0b if a function would never set the No Snoop attribute in transactions it initiates.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x0;
|
[10:10] RW/V |
PCIE_CAP_AUX_POWER_PM_EN
Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit, enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems should continue to indicate PME Aux power requirements. Aux power is allocated as requested in the Aux_Current field of the Power Management Capabilities register (PMC), independent of the PME_En bit in the Power Management Control/Status register (PMCSR). For Multi-Function devices, a component is allowed to draw Aux power if at least one of the functions has this bit set. Note: Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this bit is not modified by Conventional Reset.
For functions that do not implement this capability, the controller hardwires this bit to 0b.
Additional Aux power is permitted to be allocated using the firmware based mechanism (see the Request D3cold Aux Power Limit _DSM call as defined in [Firmware])
Additional Aux power is also permitted to be allocated by selecting a PM Sub State in the Power Limit mechanism.
Note: This register field is sticky.
Reset: hex:0x0;
|
[09:09] RO/V |
PCIE_CAP_PHANTOM_FUNC_EN
Phantom Functions Enable
This field, in combination with the PCIE_CAP_10BITS_TAG_REQ_EN field of the DEVICE_CONTROL2_DEVICE_STATUS2_REG register and the DEV3_CAP_14B_TAG_REQUEST_EN field of the DEVICE_CONTROL3_REG register, determines how many Tag field bits a Requester is permitted to use. When the PCIE_CAP_10BITS_TAG_REQ_EN field is clear the Values apply.
Behavior is undefined when this bit is Set in Functions with enabled Shadow Functions.
Software should not change the value of this field while the Function has outstanding Non-Posted Requests; otherwise, the result is undefined.
For functions that do not implement this capability, the controller hardwires this field to 0b.
For more information, see section 2.2.6.2 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
The Function is not allowed to use Phantom Functions |
| SET |
0x1 |
Enables a Function to use unclaimed Functions as Phantom Functions to extend the number of outstanding transaction identifiers |
|
[08:08] RW/V |
PCIE_CAP_EXT_TAG_EN
Extended Tag Field Enable
This field, in combination with the PCIE_CAP_10BITS_TAG_REQ_EN field of DEVICE_CONTROL2_DEVICE_STATUS2_REG register and the DEV3_CAP_14B_TAG_REQUEST_EN field of DEVICE_CONTROL3_REG register, determines how many Tag field bits a Requester is permitted to use. When the PCIE_CAP_10BITS_TAG_REQ_EN field and the DEV3_CAP_14B_TAG_REQUEST_EN field are both clear, the Values apply.
If software changes the value of the this field while the Function has outstanding Non-Posted Requests, the result is undefined. For Functions that do not implement this capability, the controller hardwires this field to 0b.
For more information, see section 2.2.6.2 of the PCI Express Base Specification for required behavior when one or both of these larger-Tag Requester Enable fields are set.
Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
The Function is restricted to use a 5-bit Tag field |
| SET |
0x1 |
The Function is permitted to use an 8-bit Tag field as a Requester |
|
[07:05] RW |
PCIE_CAP_MAX_PAYLOAD_SIZE_CS
Max_Payload_Size. For specified cases, this field determines the maximum TLP payload size (the MPS setting) for the Function. Values permitted to be programmed are indicated by the Max_Payload_Size Supported field.
As a Receiver, if the Rx_MPS_Fixed bit is Set, the Rx_MPS_Limit is fixed with the value indicated by the Max_Payload_Size Supported field. Otherwise, the Rx_MPS_Limit is determined by the MPS setting in one or more Functions. See Section 2.2.2 for important details regarding Multi Function Devices.
As a Transmitter, the Function must not generate TLPs with payloads exceeding the MPS setting, with the exception of Functions in a Multi-Function Device , or Functions with implemention-specific mechanisms capable of supporting different MPS settings for different targets. See Section 2.2.2 for important details. Defined encodings for this field are: For Functions that support only the 128-byte max payload size, the controller hardwires this field to 000b.
System software is not required to program the same value for this field for all the Functions of a Multi-Function device (for more details, see section 2.2.2 of PCI Express Base Specification).
For ARI Devices, Max_Payload_Size is determined solely by the setting in Function0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.
On an update to the Max Payload Size field, system software must ensure that no traffic which could be impacted by the change to Max Payload Size is active. Traffic that is impacted by the change to Max Payload Size can only happen after the register update is completed.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_1024B_SIZE |
0x3 |
1024 bytes MPS |
| MAX_128B_SIZE |
0x0 |
128 bytes MPS |
| MAX_2048B_SIZE |
0x4 |
2048 bytes MPS |
| MAX_256B_SIZE |
0x1 |
256 bytes MPS |
| MAX_4096B_SIZE |
0x5 |
4096 bytes MPS |
| MAX_512B_SIZE |
0x2 |
512 bytes MPS |
| RESERVED1 |
0x6 |
RESERVED |
| RESERVED2 |
0x7 |
RESERVED |
|
[04:04] RW |
PCIE_CAP_EN_REL_ORDER
Enable Relaxed Ordering. If this bit is set, the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details, see section 2.2.6.4 and section 2.4 of PCI Express Base Specification).
For a function that never sets the Relaxed Ordering attribute in transactions it initiates as a Requester, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
|
[03:03] RW |
PCIE_CAP_UNSUPPORT_REQ_REP_EN
Unsupported Request Reporting Enable. This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (for more details, see section 6.2.5 and section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each Function from point-of-view of the respective Function.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[02:02] RW |
PCIE_CAP_FATAL_ERR_REPORT_EN
Fatal Error Reporting Enable
This field, in conjunction with other field, controls sending ERR_FATAL Messages. For a Multi-Function device, this field controls error reporting for each function from point-of-view of the respective Function.
For a Root Port, the reporting of Fatal errors is internal to the root. No external ERR_FATAL Message is generated.
An RCiEP that is not associated with a Root Complex Event Collector is permitted to hardwire this field to 0b.
For PFs and VFs, see #sect-sr-iov-error-handling for details on error handling.
For more information, see section 6.2.5 and 6.2.6 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[01:01] RW |
PCIE_CAP_NON_FATAL_ERR_REPORT_EN
Non-Fatal Error Reporting Enable
This field, in conjunction with other field, controls sending ERR_NONFATAL Messages. For a Multi-Function Device, this field controls error reporting for each function from point-of-view of the respective Function.
For a Root Port, the reporting of Non-fatal errors is internal to the root. No external ERR_NONFATAL Message is generated.
An RCiEP that is not associated with a Root Complex Event Collector is permitted to hardwire this field to 0b.
For PFs and VFs, see #sect-sr-iov-error-handling for details on error handling.
For more information, see section 6.2.5 and 6.2.6 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[00:00] RW |
PCIE_CAP_CORR_ERR_REPORT_EN
Correctable Error Reporting Enable
This field, in conjunction with other field, controls sending ERR_COR Messages.
For a Multi-Function device, this field controls error reporting for each function from point-of-view of the respective Function.
For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR Message is generated.
An RCiEP that is not associated with a Root Complex Event Collector is permitted to hardwire this field to 0b.
For PFs and VFs, see #sect-sr-iov-error-handling for details on error handling.
For more information, see section 6.2.5, 6.2.6, and 6.2.10.2 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x0000007c Register(32 bit) LINK_CAPABILITIES_REG
Link Capabilities Register.
The Link Capabilities register identifies PCI Express Link specific capabilities and CXL-RCRB link specific capabilities.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100007c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00437c25 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
| Name |
PCIE_CAP_PORT_NUM |
RSVDP_23 |
PCIE_CAP_ASPM_OPT_COMPLIANCE |
PCIE_CAP_LINK_BW_NOT_CAP |
PCIE_CAP_DLL_ACTIVE_REP_CAP |
PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP |
PCIE_CAP_CLOCK_POWER_MAN |
PCIE_CAP_L1_EXIT_LATENCY |
PCIE_CAP_L0S_EXIT_LATENCY |
PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT |
PCIE_CAP_MAX_LINK_WIDTH |
PCIE_CAP_MAX_LINK_SPEED |
| Access |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO/V |
RO/V |
RO |
RO |
RO |
[31:24] RO |
PCIE_CAP_PORT_NUM
Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
Reset: hex:0x00;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:22] RO |
PCIE_CAP_ASPM_OPT_COMPLIANCE
ASPM Optionality Compliance. This field must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.
Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
Reset: hex:0x1;
|
[21:21] RO |
PCIE_CAP_LINK_BW_NOT_CAP
Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.
This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[20:20] RO |
PCIE_CAP_DLL_ACTIVE_REP_CAP
Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.
For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[19:19] RO |
PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP
Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.
For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[18:18] RO |
PCIE_CAP_CLOCK_POWER_MAN
Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) through the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.
L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.
This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.
For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.
Note: The controller does not support this feature with PIPE 4.2 configuration if L1 Substate is not enabled.
For Downstream Ports, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[17:15] RO/V |
PCIE_CAP_L1_EXIT_LATENCY
L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined.
Note: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.
There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request. Common Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x6;
| Valid Values |
| Name | Value(s) | Description |
| GREATER_THAN_64US |
0x7 |
More than 64 us |
| LESS_THAN_1US |
0x0 |
Less than 1us |
| _16US_TO_32US |
0x5 |
16 us to less than 32 us |
| _1US_TO_2US |
0x1 |
1 us to less than 2 us |
| _2US_TO_4US |
0x2 |
2 us to less than 4 us |
| _32US_TO_64US |
0x6 |
32 us to 64 us |
| _4US_TO_8US |
0x3 |
4 us to less than 8 us |
| _8US_TO_16US |
0x4 |
8 us to less than 16 us |
|
[14:12] RO/V |
PCIE_CAP_L0S_EXIT_LATENCY
L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; however, see the Implementation Note "Potential Issues With Legacy Software When L0s is Not Supported" in section 5.4.1.1 of PCI Express Base Specification for the recommended value.
Note: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.
There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request. Common Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x7;
| Valid Values |
| Name | Value(s) | Description |
| GREATER_THAN_4US |
0x7 |
More than 4 us |
| LESS_THAN_64NS |
0x0 |
Less than 64 ns |
| _128NS_TO_256NS |
0x2 |
128 ns to less than 256 ns |
| _1US_TO_2US |
0x5 |
1 us to less than 2 us |
| _256NS_TO_512NS |
0x3 |
256 ns to less than 512 ns |
| _2US_TO_4US |
0x6 |
2 us to 4 us |
| _512NS_TO_1US |
0x4 |
512 ns to less than 1 us |
| _64NS_TO_128NS |
0x1 |
64 ns to less than 128 ns |
|
[11:10] RO |
PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT
Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more information on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification. Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| L0S_L1_SUP |
0x3 |
L0s and L1 Supported |
| L0S_SUP |
0x1 |
L0s Supported |
| L1_SUP |
0x2 |
L1 Supported |
| NO_ASPM_SUP |
0x0 |
No ASPM Support |
|
[09:04] RO |
PCIE_CAP_MAX_LINK_WIDTH
Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width. All encodings other than the defined encodings are reserved. Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x02;
| Valid Values |
| Name | Value(s) | Description |
| X1 |
0x1 |
x1 |
| X16 |
0x10 |
x16 |
| X2 |
0x2 |
x2 |
| X4 |
0x4 |
x4 |
| X8 |
0x08 |
x8 |
|
[03:00] RO |
PCIE_CAP_MAX_LINK_SPEED
Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed. All encodings other than the defined encodings are reserved.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x5;
| Valid Values |
| Name | Value(s) | Description |
| SUP_LINK_SPEED_FIELD_BIT_0 |
0x1 |
Supported Link Speeds Vector field bit 0 |
| SUP_LINK_SPEED_FIELD_BIT_1 |
0x2 |
Supported Link Speeds Vector field bit 1 |
| SUP_LINK_SPEED_FIELD_BIT_2 |
0x3 |
Supported Link Speeds Vector field bit 2 |
| SUP_LINK_SPEED_FIELD_BIT_3 |
0x4 |
Supported Link Speeds Vector field bit 3 |
| SUP_LINK_SPEED_FIELD_BIT_4 |
0x5 |
Supported Link Speeds Vector field bit 4 |
| SUP_LINK_SPEED_FIELD_BIT_5 |
0x6 |
Supported Link Speeds Vector field bit 5 |
| SUP_LINK_SPEED_FIELD_BIT_6 |
0x7 |
Supported Link Speeds Vector field bit 6 |
|
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+0x00000080 Register(32 bit) LINK_CONTROL_LINK_STATUS_REG
Link Control and Link Status Register.
This register controls and provides information about PCI Express Link specific parameters as well as RCRB link associated parameters.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000080 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x10110000 |
|
|
Unaffected |
0x0bff3d30 |
|
|
Undefined |
0x00003000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PCIE_CAP_LINK_AUTO_BW_STATUS |
PCIE_CAP_LINK_BW_MAN_STATUS |
PCIE_CAP_DLL_ACTIVE |
PCIE_CAP_SLOT_CLK_CONFIG |
PCIE_CAP_LINK_TRAINING |
RSVDP_26 |
PCIE_CAP_NEGO_LINK_WIDTH |
PCIE_CAP_LINK_SPEED |
PCIE_CAP_DRS_SIGNALING_CONTROL |
- |
PCIE_CAP_LINK_AUTO_BW_INT_EN |
PCIE_CAP_LINK_BW_MAN_INT_EN |
PCIE_CAP_HW_AUTO_WIDTH_DISABLE |
PCIE_CAP_EN_CLK_POWER_MAN |
PCIE_CAP_EXTENDED_SYNCH |
PCIE_CAP_COMMON_CLK_CONFIG |
PCIE_CAP_RETRAIN_LINK |
PCIE_CAP_LINK_DISABLE |
PCIE_CAP_RCB |
RSVDP_2 |
PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL |
| Access |
RO |
RO |
RO |
RO |
RO/V |
RO |
RO/V |
RO/V |
RO |
- |
RW/V |
RW/V |
RW |
RW/V |
RW/V |
RW |
RW/V |
RW/V |
RW |
RO |
RW |
[31:31] RO |
PCIE_CAP_LINK_AUTO_BW_STATUS
Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation.
This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change.
The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.
For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R
Reset: hex:0x0;
|
[30:30] RO |
PCIE_CAP_LINK_BW_MAN_STATUS
Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status:
A Link retraining has completed following a write of 1b to the Retrain Link bit.
Note: This bit is set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason.
Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process.
This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change. This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.
For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b. The default value of this bit is 0b.
The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R
Reset: hex:0x0;
|
[29:29] RO |
PCIE_CAP_DLL_ACTIVE
Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.
This bit must be implemented if the Data Link Layer Link Active Reporting Capable bit is 1b. Otherwise, the controller hardwires it to 0b.
Reset: hex:0x0;
|
[28:28] RO |
PCIE_CAP_SLOT_CLK_CONFIG
Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear.
For a Multi-Function Device, each Function must report the same value for this bit.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
Reset: hex:0x1;
|
[27:27] RO/V |
PCIE_CAP_LINK_TRAINING
Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.
This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and the controller hardwires it to 0b.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R
Reset: hex:0x0;
|
[26:26] RO |
RSVDP_26
Reserved for future use.
Reset: hex:0x0;
|
[25:20] RO/V |
PCIE_CAP_NEGO_LINK_WIDTH
Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link.This includes the Link Width determined during initial link training as well changes that occur afer initial link training (e.g., L0p). All encodings other than the defined encodings are reserved. The value in this field is undefined when the Link is not up.
Reset: hex:0x01;
| Valid Values |
| Name | Value(s) | Description |
| X1 |
0x1 |
x1 |
| X16 |
0x10 |
x16 |
| X2 |
0x2 |
x2 |
| X4 |
0x4 |
x4 |
| X8 |
0x08 |
x8 |
|
[19:16] RO/V |
PCIE_CAP_LINK_SPEED
Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed. All encodings other than the defined encodings are reserved. The value in this field is undefined when the Link is not up.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| SUP_LINK_SPEED_FIELD_BIT_0 |
0x1 |
Supported Link Speeds Vector field bit 0 |
| SUP_LINK_SPEED_FIELD_BIT_1 |
0x2 |
Supported Link Speeds Vector field bit 1 |
| SUP_LINK_SPEED_FIELD_BIT_2 |
0x3 |
Supported Link Speeds Vector field bit 2 |
| SUP_LINK_SPEED_FIELD_BIT_3 |
0x4 |
Supported Link Speeds Vector field bit 3 |
| SUP_LINK_SPEED_FIELD_BIT_4 |
0x5 |
Supported Link Speeds Vector field bit 4 |
| SUP_LINK_SPEED_FIELD_BIT_5 |
0x6 |
Supported Link Speeds Vector field bit 5 |
| SUP_LINK_SPEED_FIELD_BIT_6 |
0x7 |
Supported Link Speeds Vector field bit 6 |
|
[15:14] RO |
PCIE_CAP_DRS_SIGNALING_CONTROL
DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are:
If DRS Supported is set, receiving a DRS Message will set DRS Message Received in the Link Status 2 Register but will otherwise have no effect
If the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, and either MSI or MSI-X is enabled, an MSI or MSI-X interrupt is generated using the vector in Interrupt Message Number (section 7.5.3.2)
If the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, the Port must send an FRS Message Upstream with the FRS Reason field set to DRS Message Received.
Behavior is undefined if this field is set to 10b and the FRS Supported bit in the Device Capabilities 2 Register is Clear.
Behavior is undefined if this field is set to 11b. For Downstream Ports with the DRS Supported bit clear in the Link Capabilities 2 register, the controller hardwires this field to 00b. This field is Reserved for Upstream Ports.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DRS_INTRRUPT_EN |
0x1 |
DRS Interrupt Enabled |
| DRS_NOT_REPORTED |
0x0 |
DRS not Reported |
| FRS_EN |
0x2 |
DRS to FRS Signaling Enabled |
|
[11:11] RW/V |
PCIE_CAP_LINK_AUTO_BW_INT_EN
Link Autonomous Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.
For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
Reset: hex:0x0;
|
[10:10] RW/V |
PCIE_CAP_LINK_BW_MAN_INT_EN
Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.
For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
Reset: hex:0x0;
|
[09:09] RW |
PCIE_CAP_HW_AUTO_WIDTH_DISABLE
Hardware Autonomous Width Disable. When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.
For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.
For components that do not implement the ability autonomously to change Link width, the ciontroller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[08:08] RW/V |
PCIE_CAP_EN_CLK_POWER_MAN
Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a "Clock Request" (CLKREQ#) mechanism, this bit operates as follows: For a non-ARI Multi-Function Device, power-management-configuration software must only Set this bit if all Functions of the Multi-Function Device indicate a 1b in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage Link clock only if this bit is Set for all Functions.
For ARI Devices, Clock Power Management is enabled solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component. The CLKREQ# signal may also be controlled through the L1 PM Substates mechanism. Such control is not affected by the setting of this bit.
For Downstream Ports and components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities register), the controller hardwires this bit to 0b.
The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.
Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLKREQ_IN_USE |
0x1 |
When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according to protocol defined in appropriate form factor specification. |
| PM_DISABLE_LOW_CLKREQ |
0x0 |
Clock power management is disabled and device must hold CLKREQ# signal low. |
|
[07:07] RW/V |
PCIE_CAP_EXTENDED_SYNCH
Extended Synch
This mode provides external devices (for example, logic analyzers) monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication.
For Multi-Function devices if any function has this field set, then the component must transmit the additional Ordered Sets when exiting L0s or when in Recovery.
In Flit Mode, this field is ignored and has no effect since L0s is not supported.
For more information, see section 4.2.4.5 and 4.2.6.4.1 of the PCI Express Base Specification.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This field forces the transmission of additional Ordered Sets when exiting the L0s state and when in the Recovery state. |
| CLEAR |
0x0 |
Clear |
|
[06:06] RW |
PCIE_CAP_COMMON_CLK_CONFIG
Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.
A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.
For non-ARI Multi-Function Devices, software must program the same value for this bit in all Functions. If not all Functions are Set, then the component must as a whole assume that its reference clock is not common with the Upstream component.
For ARI Devices, Common Clock Configuration is determined solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.
Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies.
After changing the value in this bit in both components on a Link, software must trigger the Link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port.
Reset: hex:0x0;
|
[05:05] RW/V |
PCIE_CAP_RETRAIN_LINK
Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. If the Port is in DPC when a write of 1b to this bit occurs, the result is undefined. Reads of this bit always return 0b.
It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.
This bit is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
This bit always returns 0b when read.
Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description
Reset: hex:0x0;
|
[04:04] RW/V |
PCIE_CAP_LINK_DISABLE
Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.
After clearing this bit, software must honor timing requirements defined in Section 6.6.1 with respect to the first Configuration Read following a Conventional Reset.
In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.
Note: The access attributes of this field are as follows: - Wire: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1 ? RW : RO - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
Reset: hex:0x0;
|
[03:03] RW |
PCIE_CAP_RCB
Read Completion Boundary (RCB).
Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. The controller hardwires this bit for a Root Port and returns its RCB support capabilities.
Endpoints and Bridges: Optionally set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Refer to Section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB is same as Root Port. Configuration software must only set this bit if the Root Port Upstream from the Endpoint or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion Boundary bit). For functions that do not implement this feature, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _128B |
0x1 |
128 byte |
| _64B |
0x0 |
64 byte |
|
[02:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x0;
|
[01:00] RW |
PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL
ASPM Control/Active State Power Management Control
This field controls the level of ASPM enabled on the given PCI Express Link.
For requirements on when and how to enable ASPM, see section 5.4.1.3 of the PCI Express Base Specification.
Note: "L0s Entry Enabled" enables the Transmitter to enter L0s. If L0s is supported, the Receiver must be capable of entering L0s even when the Transmitter is disabled from entering L0s (00b or 10b).
In Flit Mode, L0s is not supported, bit 0 of this field is ignored and has no effect (that is, encodings 0x1 and 0x0 are equivalent as are encodings 0x3 and 0x2).
ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link. When disabling ASPM L1, software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link. ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1.
For Multi-Function Devices (including ARI Devices), it is recommended that software program the same value for this field in all Functions. For non-ARI Multi-Function Devices, only capabilities enabled in all Functions are enabled for the component as a whole.
For ARI Devices, ASPM Control is determined solely by the setting in Function0, regardless of Function 0's D-state. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component. Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise, the result is undefined.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLED |
0x0 |
Disabled |
| L0S_ENTRY_EN |
0x1 |
L0s Entry Enabled |
| L0S_L1_ENTRY_EN |
0x3 |
L0s and L1 Entry Enabled |
| L1_ENTRY_EN |
0x2 |
L1 Entry Enabled |
|
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+0x00000094 Register(32 bit) DEVICE_CAPABILITIES2_REG
Device Capabilities 2 Register.
This register identifies PCI Express device specific capabilities; in addition to the Device Capabilities Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000094 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00b10010 |
|
|
Unaffected |
0x870c3800 |
|
|
Undefined |
0x870c3800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
0 |
0 |
0 |
0 |
- |
- |
- |
1 |
0 |
1 |
1 |
- |
- |
0 |
1 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| Name |
- |
PCIE_CAP_DMWR_LEN_SUPP |
PCIE_CAP_DMWR_CPL_SUPP |
RSVDP_27 |
- |
PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS |
PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT |
PCIE_CAP2_CFG_EXTND_FMT_SUPPORT |
- |
PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT |
PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT |
PCIE_CAP2_LN_SYS_CLS |
- |
PCIE_CAP_NO_RO_EN_PR2PR_PAR |
PCIE_CAP_128_CAS_CPL_SUPP |
PCIE_CAP_64_ATOMIC_CPL_SUPP |
PCIE_CAP_32_ATOMIC_CPL_SUPP |
PCIE_CAP_ATOMIC_ROUTING_SUPP |
PCIE_CAP_ARI_FORWARD_SUPPORT |
PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT |
PCIE_CAP_CPL_TIMEOUT_RANGE |
| Access |
- |
RO |
RO |
RO |
- |
RO |
RO |
RO |
- |
RO |
RO |
RO/V |
- |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
[30:29] RO |
PCIE_CAP_DMWR_LEN_SUPP
Deferrable Memory Write (DMWr) Lengths Supported. Applicable to Functions with either the DMWr Routing Supported bit Set or the DMWR Completer Supported bit Set (or both). This field indicates the largest DMWr TLP that this Function can receive. When applicable, all Functions in a Multi-Function Device associated with an Upstream Port must report the same value in this field. This field is RsvdP if both DMWr Completer Supported and DMWr Routing Supported are Clear. For more information, see Section 6.30 of PCI Express Base Specification.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| up_to_128_bytes |
0x1 |
1 up to 128 bytes |
| up_to_64_bytes |
0x0 |
0 up to 64 bytes |
|
[28:28] RO |
PCIE_CAP_DMWR_CPL_SUPP
Deferrable Memory Write (DMWr) Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; This bit must be Set if the Function can serve as a DMWr Completer. For more information, see Section 6.30 of PCI Express Base Specification.
Reset: hex:0x0;
|
[27:27] RO |
RSVDP_27
Reserved for future use.
Reset: hex:0x0;
|
[23:22] RO |
PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS
Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function (NFM) or the maximum size of OHC-E supported (FM). For more information, see Section 2.2.10.2 of PCI Express Base Specification. If End-End TLP Prefix Supported is clear, this field is RsvdP.
Different Root Ports that have the End-End TLP Prefix Supported bit set are permitted to report different values for this field.
For Switches where End-End TLP Prefix Supported is set, this field must be 00b indicating support for up to four End-End TLP Prefixes.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| FOUR_END_END_TLP_PREFIX |
0x0 |
4 End-End TLP Prefixes OHC-E4 |
| ONE_END_END_TLP_PREFIX |
0x1 |
1 End-End TLP Prefix OHC-E1 |
| THREE_END_END_TLP_PREFIX |
0x3 |
3 End-End TLP Prefixes OHC-E3 |
| TWO_END_END_TLP_PREFIX |
0x2 |
2 End-End TLP Prefixes OHC-E2 |
|
[21:21] RO |
PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT
End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support (NFM) / OHC-E (FM) is offered by a Function. Values are: All Ports of a Switch must have the same value for this bit.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUP |
0x0 |
No Support |
| SUP |
0x1 |
Support is provided to receive TLPs containing End-End TLP Prefixes (NFM) or OHC-E (FM). |
|
[20:20] RO |
PCIE_CAP2_CFG_EXTND_FMT_SUPPORT
Extended Fmt Field Supported
If Set, the Function supports the 3-bit definition of the Fmt field when operating in Non-Flit Mode. If Clear, the Function supports a 2-bit definition of the Fmt field.
Must be set for Functions that support End-End TLP Prefixes (NFM) or OHC-E (FM). All Functions in an Upstream Port must have the same value for this field. Each Downstream Port of a component may have a different value for this field.
MUST@FLIT be Set.
For more information, see section 2.2 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
The Function supports a 2-bit definition of the Fmt field. |
| SET |
0x1 |
The Function supports the 3-bit definition of the Fmt field when operating in Non-Flit Mode. |
|
[17:17] RO |
PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT
10-Bit Tag Requester Supported
This field must not be set if the PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT field is clear.
Note: 10-Bit Tag field generation must be enabled by the PCIE_CAP_10BITS_TAG_REQ_EN field in the DEVICE_CONTROL2_DEVICE_STATUS2_REG register of the Requester Function before 10-Bit Tags can be generated by the Requester.
For VFs, this bit value must equal the VF 10-Bit Tag Requester Supported bit value in the SR-IOV Capabilities register.
For more information, see section 2.2.6.2. of the PCI Express Base Specification.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
The Function does not support 10-Bit Tag Requester capability. |
| SET |
0x1 |
The Function supports 10-Bit Tag Requester capability. |
|
[16:16] RO |
PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT
10-Bit Tag Completer Supported
For VFs, this field value must be identical to the associated PF's field value.
For more information, see section 2.2.6.2. of the PCI Express Base Specification.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
The Function does not support 10-Bit Tag Completer capability |
| SET |
0x1 |
The Function supports 10-Bit Tag Completer capability |
|
[15:14] RO/V |
PCIE_CAP2_LN_SYS_CLS
LN System CLS. Applicable only to Root Ports and RCRBs; must be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect. All encodings other than the defined encodings are reserved.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| LN_COMPLETER_128B_CACHE |
0x2 |
LN Completer with 128-byte cachelines in effect |
| LN_COMPLETER_64B_CACHE |
0x1 |
LN Completer with 64-byte cachelines in effect |
| LN_COMPLETER_NO_SUP |
0x0 |
LN Completer either not supported or not in effect |
|
[10:10] RO |
PCIE_CAP_NO_RO_EN_PR2PR_PAR
No RO-enabled PR-PR Passing. If this bit is set, the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute field being Set. This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit. For all other functions, this bit must be 0b.
Reset: hex:0x0;
|
[09:09] RO |
PCIE_CAP_128_CAS_CPL_SUPP
128-bit CAS Completer Supported Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This field must be set to 1b if the Function supports this optional capability.
For VFs, this field value must be identical to the associated PF's field value.
For more information, see section 6.15 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[08:08] RO |
PCIE_CAP_64_ATOMIC_CPL_SUPP
64-bit AtomicOp Completer Supported Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability.
For VFs, this field value must be identical to the associated PF's field value.
For more information on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[07:07] RO |
PCIE_CAP_32_ATOMIC_CPL_SUPP
32-bit AtomicOp Completer Supported
Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This field must be set to 1b if the Function supports this optional capability.
For VFs, this field value must be identical to the associated PF's field value.
For more information on additional RC requirements, see section 6.15.3.1 of the PCI Express Base Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[06:06] RO |
PCIE_CAP_ATOMIC_ROUTING_SUPP
AtomicOp Routing Supported. Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For more information, see section 6.15 of PCI Express Base Specification.
Reset: hex:0x0;
|
[05:05] RO |
PCIE_CAP_ARI_FORWARD_SUPPORT
ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. For more information, see section 6.13 of PCI Express Base Specification.
Reset: hex:0x0;
|
[04:04] RO |
PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT
Completion Timeout Disable Supported
The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.
For VFs, this field value must be identical to the associated PF's field value.
This mechanism is optional for Root Ports.
For all other Functions this field is reserved and the controller hardwires this field to 0b.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates support for the Completion Timeout Disable mechanism. |
| CLEAR |
0x0 |
Clear |
|
[03:00] RO |
PCIE_CAP_CPL_TIMEOUT_RANGE
Completion Timeout Ranges Supported
This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is reserved and must be hardwired to 0000b.
Four time value ranges are defined (A, B, C, D), each with two selectable sub-ranges (for which the time ranges are defined in the description of the Completion Timeout Value field in the Device Control 2 register):
The value in this field indicates the timeout value ranges supported.
For VFs, this field value must be identical to the associated PF's field value.
Undefined encodings: Reserved
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NOT_SUP |
0x0 |
Completion Timeout programming not supported. |
| RANGE_A |
0x1 |
Range A |
| RANGE_A_B |
0x3 |
Ranges A and B |
| RANGE_A_B_C |
0x7 |
Ranges A, B, and C |
| RANGE_A_B_C_D |
0x0f |
Ranges A, B, C, and D |
| RANGE_B |
0x2 |
Range B |
| RANGE_B_C |
0x6 |
Ranges B and C |
| RANGE_B_C_D |
0x0e |
Ranges B, C, and D |
|
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+0x00000098 Register(32 bit) DEVICE_CONTROL2_DEVICE_STATUS2_REG
Device Control 2 and Status 2 Register.
This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters; in addition to the Device Control and Device Status Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000098 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x00007fc0 |
|
|
Undefined |
0x00007fc0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_16 |
PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK |
- |
PCIE_CAP_ARI_FORWARD_SUPPORT_CS |
PCIE_CAP_CPL_TIMEOUT_DISABLE |
PCIE_CAP_CPL_TIMEOUT_VALUE |
| Access |
RO |
RO |
- |
RO |
RW |
RO |
[31:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0000;
|
[15:15] RO |
PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK
End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix (NFM)/OHC-E (FM). This bit affects TLPs that exit the Switch/Root Complex using the associated Port. It does not affect TLPs forwarded internally within the Switch/Root Complex. It does not affect TLPs that enter through the associated Port, that originate in the associated Port or originate in a Root Complex Integrated Device integrated with the associated Port. Blocked TLPs are reported by the TLP Prefix Blocked Error.
This bit is hardwired to 1b in Root Ports that support End-End TLP Prefixes/OHC-E but do not support forwarding of End-End TLP Prefixes/OHC-E.
This bit is applicable to Root Ports and Switch Ports where the End-End TLP Prefix Supported bit is set. This bit is not applicable and is RsvdP in all other cases.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FORWARDING_BL |
0x1 |
Forwarding Blocked, Function is not permitted to send TLPs with End-End TLP Prefixes (NFM) or OHC-E (FM. |
| FORWARDING_EN |
0x0 |
Forwarding Enabled, Function is permitted to send TLPs with End-End TLP Prefixes (NFM) or OHC-E (FM). |
|
[05:05] RO |
PCIE_CAP_ARI_FORWARD_SUPPORT_CS
ARI Forwarding Enable. When set, the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. For more information, see Section 6.13 of PCI Express Base Specification.
Reset: hex:0x0;
|
[04:04] RW |
PCIE_CAP_CPL_TIMEOUT_DISABLE
Completion Timeout Disable For non-VFs, this field is required for all Functions that support the Completion Timeout Disable Capability. For VFs, the associated PF's value applies, and this field must be reserved. Otherwise, Functions that do not support this optional capability are permitted to hardwire this bit to 0b. Software is permitted to set or clear this field at any time. If there are outstanding Requests when the field is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding Requests. If this is done, it is permitted to base the start time for each Request on either the time this field was cleared or the time each Request was issued.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Disables the Completion Timeout mechanism |
| CLEAR |
0x0 |
Clear |
|
[03:00] RO |
PCIE_CAP_CPL_TIMEOUT_VALUE
Completion Timeout Value In device Functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value.
This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For VFs, the associated PF's value applies, and this field must be RsvdP . For all other Functions, this field is Reserved and controller hardwires it to 0000b.
A Function that does not support this optional capability must hardwire this field to 0000b and MUST@FLIT implement a timeout value in the range 40 ms to 50 ms. A function that does not support Flit Mode must to implement a timeout value in the range 50 us to 50 ms. Functions that support Completion Timeout programmability must support the values given below corresponding to the programmability ranges indicated in the Completion Timeout Ranges Supported field.
For Functions that do not support Flit Mode, it is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.
Software is permitted to change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding Requests, and is permitted to base the start time for each Request either on when this value was changed or on when each request was issued.
Undefined encodings: Reserved.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DEFAULT |
0x0 |
Default range: 50 us to 50 ms; the Function MUST@FLIT implement a timeout value in the range 40 ms to 50 ms. |
| _16_TO_55_MS |
0x5 |
16 ms to 55 ms; Available values for Range B |
| _17_TO_64_S |
0x0e |
17 s to 64 s; Available values for Range D |
| _1_TO_10_MS |
0x2 |
1 ms to 10 ms; Available values for Range A |
| _1_TO__3_5_S |
0x0a |
1 s to 3.5 s; Available values for Range C |
| _260_TO_900_MS |
0x09 |
260 ms to 900 ms; Available values for Range C |
| _4_TO_13_S |
0x0d |
4 s to 13 s; Available values for Range D |
| _50_TO_100_US |
0x1 |
50 us to 100 us; Available values for Range A |
| _65_TO_210_MS |
0x6 |
65 ms to 210 ms; Available values for Range B |
|
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+0x0000009c Register(32 bit) LINK_CAPABILITIES2_REG
Link Capabilities 2 Register.
This register identifies PCI Express Link specific capabilities and CXL-RCRB link specific capabilities; in addition to the Link Capabilities Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100009c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x0180003e |
|
|
Unaffected |
0x807ffefe |
|
|
Undefined |
0x80000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
| Name |
- |
RSVDP_25 |
PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT |
PCIE_CAP_RETIMER_PRE_DET_SUPPORT |
PCIE_CAP_LWR_SKP_OS_RCV_SUP |
PCIE_CAP_LWR_SKP_OS_GEN_SUP |
PCIE_CAP_CROSS_LINK_SUPPORT |
PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR |
RSVDP_0 |
| Access |
- |
RO |
RW/V |
RO |
RO/V |
RO/V |
RO |
RO/V |
RO |
[30:25] RO |
RSVDP_25
Reserved for future use.
Reset: hex:0x00;
|
[24:24] RW/V |
PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT
Two Retimers Presence Detect Supported When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.
This bit MUST@FLIT be Set.
This bit must be set to 1b in a Port when the PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR of the LINK_CAPABILITIES2_REG register indicates support for a Link speed of 16.0 GT/s or higher. It is permitted to be set to 1b regardless of the supported Link speeds if the PCIE_CAP_RETIMER_PRE_DET_SUPPORT field is also set to 1b.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Reset: hex:0x1;
|
[23:23] RO |
PCIE_CAP_RETIMER_PRE_DET_SUPPORT
Retimer Presence Detect Supported When set to 1b, this field indicates that the associated Port supports detection and reporting of Retimer presence.
This bit MUST@FLIT be Set.
This bit must be set to 1b in a Port when the PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR of the LINK_CAPABILITIES2_REG register indicates support for a Link speed of 16.0 GT/s or higher. It is permitted to be set to 1b regardless of the supported Link speeds.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Reset: hex:0x1;
|
[22:16] RO/V |
PCIE_CAP_LWR_SKP_OS_RCV_SUP
Lower SKP OS Reception Supported Speeds Vector If this field is non-Zero, it indicates that the port, when operating at the indicated speed supports SRIS and also supports receiving SKP OS at the rate defined for SRNS while running in SRIS.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions. Behavior is undefined if a bit is set to '1' in this field and the corresponding bit is not set to '1' in the PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR field.
This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0110) ? 0111111 :(PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| DEF_LAST_VALUE |
0x7f |
Default last value; Multi-Function Device |
| INITIAL_VALUE |
0x0 |
Zero value |
| RSVD1 |
0x6 |
Reserved |
| RSVD2 |
0x7 |
Reserved |
| _16GTs |
0x3 |
16 GT/s |
| _2_5GTs |
0x0 |
2.5 GT/s |
| _32GTs |
0x4 |
32 GT/s |
| _5GTs |
0x1 |
5 GT/s |
| _64GTs |
0x5 |
64 GT/s |
| _8GTs |
0x2 |
8 GT/s |
|
[15:09] RO/V |
PCIE_CAP_LWR_SKP_OS_GEN_SUP
Lower SKP OS Generation Supported Speeds Vector If this field is non-Zero, it indicates that the port, when operating at the indicated speed supports SRIS and also supports software control of the SKP Ordered Set transmission scheduling rate.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions. Behavior is undefined if a bit is set to '1' in this field and the corresponding bit is not set to '1' in the PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR field.
This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0110) ? 0111111 :(PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| DEFAULT_LAST_VALUE |
0x7f |
Default last value; Multi-Function Device |
| INITIAL_VALUE |
0x0 |
Zero value; Multi-Function Device |
| RSVD1 |
0x6 |
Reserved |
| RSVD2 |
0x7 |
Reserved |
| _16GTs |
0x3 |
16 GT/s |
| _2_5GTs |
0x0 |
2.5 GT/s |
| _32GTs |
0x4 |
32 GT/s |
| _5GTs |
0x1 |
5 GT/s |
| _64GTs |
0x5 |
64 GT/s |
| _8GTs |
0x2 |
8 GT/s |
|
[08:08] RO |
PCIE_CAP_CROSS_LINK_SUPPORT
Crosslink Supported. When set to 1b, this bit indicates that the associated Port supports crosslinks (for more details, see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link speeds of 8.0 GT/s or higher, this bit indicates that the associated Port does not support crosslinks. When set to 0b on a Port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, this bit provides no information regarding the Port's level of crosslink support. It is recommended that this bit be Set in any Port that supports crosslinks even though doing so is only required for Ports that also support operating at 8.0 GT/s or higher Link speeds.
Note: Software should use this bit when referencing fields whose definition depends on whether or not the Port supports crosslinks (for more details, see section 7.7.3.4 of PCI Express Base Specification).
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.
Reset: hex:0x0;
|
[07:01] RO/V |
PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR
Supported Link Speeds Vector This field indicates the supported Link speeds of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.
This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0110) ? 0111111 :(PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.
For more information, see section 8.2.1 of the PCI Express Base Specification.
Reset: hex:0x1f;
| Valid Values |
| Name | Value(s) | Description |
| DEF_LAST_VALUE |
0x7f |
Default last value; Multi-Function Devices |
| INITIAL_VALUE |
0x0 |
Zero value; Multi-Function Devices |
| RSVD1 |
0x6 |
Reserved |
| RSVD2 |
0x7 |
Reserved |
| _16GTs |
0x3 |
16 GT/s |
| _2_5GTs |
0x0 |
2.5 GT/s |
| _32GTs |
0x4 |
32 GT/s |
| _5GTs |
0x1 |
5 GT/s |
| _64GTs |
0x5 |
64 GT/s |
| _8GTs |
0x2 |
8 GT/s |
|
[00:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x0;
|
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+0x000000a0 Register(32 bit) LINK_CONTROL2_LINK_STATUS2_REG
Link Control 2 and Status 2 Register.
This register controls and provides information about PCI Express Link specific parameters as well as RCRB link associated parameters; in addition to the Link Control and Link Status Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010000a0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x01010005 |
|
|
Unaffected |
0xf4000000 |
|
|
Undefined |
0xf4000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
0 |
- |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
| Name |
- |
RSVDP_27 |
- |
PCIE_CAP_CROSSLINK_RESOLUTION |
PCIE_CAP_TWO_RETIMERS_PRE_DET |
PCIE_CAP_RETIMER_PRE_DET |
PCIE_CAP_LINK_EQ_REQ |
PCIE_CAP_EQ_CPL_P3 |
PCIE_CAP_EQ_CPL_P2 |
PCIE_CAP_EQ_CPL_P1 |
PCIE_CAP_EQ_CPL |
PCIE_CAP_CURR_DEEMPHASIS |
PCIE_CAP_COMPLIANCE_PRESET |
PCIE_CAP_COMPLIANCE_SOS |
PCIE_CAP_ENTER_MODIFIED_COMPLIANCE |
PCIE_CAP_TX_MARGIN |
PCIE_CAP_SEL_DEEMPHASIS |
PCIE_CAP_HW_AUTO_SPEED_DISABLE |
PCIE_CAP_ENTER_COMPLIANCE |
PCIE_CAP_TARGET_LINK_SPEED |
| Access |
- |
RO |
- |
RO/V |
RO/V |
RO/V |
RW/1C/V |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
RW/V |
RW/V |
RW |
RW/V |
RO |
RW |
RW/V |
RW |
[27:27] RO |
RSVDP_27
Reserved for future use.
Reset: hex:0x0;
|
[25:24] RO/V |
PCIE_CAP_CROSSLINK_RESOLUTION
Crosslink Resolution. This field indicates the state of the Crosslink negotiation. It must be implemented if Crosslink Supported is Set and the Port supports 16.0 GT/s or higher data rate. It is permitted to be implemented in all other Ports. If Crosslink Supported is clear, the controller hardwires this field to 01b or 10b. Once a value of 01b or 10b is returned in this field, that value must continue to be returned while the Link is Up.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| CROSSLINK_NEGOTIATION_NOT_CMPL |
0x3 |
Crosslink negotiation is not completed. |
| CROSSLINK_NEGOTIATION_RESOLVED_DSP |
0x2 |
Crosslink negotiation resolved as a Downstream Port. |
| CROSSLINK_NEGOTIATION_RESOLVED_USP |
0x1 |
Crosslink negotiation resolved as an Upstream Port. |
| CROSSLINK_RESOLUTION_NOT_SUP |
0x0 |
Crosslink Resolution is not supported. No information is provided regarding the status of the Crosslink negotiation. |
|
[23:23] RO/V |
PCIE_CAP_TWO_RETIMERS_PRE_DET
Two Retimers Presence Detected. When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. For more information, see section 4.2.6.3.5.1 of PCI Express Base Specification.
This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.
Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.
For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and RsvdZ in all other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
|
[22:22] RO/V |
PCIE_CAP_RETIMER_PRE_DET
Retimer Presence Detected
This field is required for Ports that have the PCIE_CAP_RETIMER_PRE_DET_SUPPORT field of the LINK_CAPABILITIES2_REG register set to 1b.
For Ports that have the PCIE_CAP_RETIMER_PRE_DET_SUPPORT field set to 0b, the controller hardwires this field to 0b.
For Multi-Function Devices associated with an Upstream Port, this field must be implemented in Function 0 and is reserved in all other Functions.
For more information, see section 4.2.6.3.5.1 of the PCI Express Base Specification.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates that a Retimer was present during the most recent Link negotiation. |
| CLEAR |
0x0 |
Clear |
|
[21:21] RW/1C/V |
PCIE_CAP_LINK_EQ_REQ
Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more information, see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification.
For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[20:20] RO/V |
PCIE_CAP_EQ_CPL_P3
EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.
For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[19:19] RO/V |
PCIE_CAP_EQ_CPL_P2
Equalization 8.0 GT/s Phase 2 Successful. When set to 1b, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.
For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[18:18] RO/V |
PCIE_CAP_EQ_CPL_P1
Equalization 8.0 GT/s Phase 1 Successful. When set to 1b, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.
For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[17:17] RO/V |
PCIE_CAP_EQ_CPL
Equalization 8.0 GT/s Complete. When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.
For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[16:16] RO/V |
PCIE_CAP_CURR_DEEMPHASIS
Current De-emphasis Level When the Link is operating at 5.0 GT/s speed, this field reflects the level of de-emphasis.
The value in this field is undefined when the Link is not operating at 5.0 GT/s speed.
For VFs, the associated PF's value applies, and this field must be reserved. Otherwise, components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0b.
For components that support speeds greater than 2.5 GT/s, Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions of the Port.
In C-PCIe mode, its contents are derived by sampling the PIPE.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| _3_5DB |
0x1 |
-3.5 dB |
| _6DB |
0x0 |
-6 dB |
|
[15:12] RW/V |
PCIE_CAP_COMPLIANCE_PRESET
Compliance Preset/De-emphasis. - For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in section 4.2.3.2 of PCI Express Base Specification . Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way. - For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. - When the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b. - For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP. - This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _3_5_DB |
0x1 |
-3.5 dB (for 5.0 GT/s Data Rate) |
| _6_DB |
0x0 |
-6 dB (for 5.0 GT/s Data Rate) |
|
[11:11] RW/V |
PCIE_CAP_COMPLIANCE_SOS
Compliance SOS. When set to 1b, the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern.
For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.
This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.
For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[10:10] RW |
PCIE_CAP_ENTER_MODIFIED_COMPLIANCE
Enter Modified Compliance. When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.
For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.
This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[09:07] RW/V |
PCIE_CAP_TX_MARGIN
Transmit Margin, This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base Specification for details of how the Transmitter voltage level is determined in various states). - 001b-111b: As defined in Section 8.3.4 not all encodings are required to be implemented. For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.
For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 000b.
This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NORMAL_RANGE |
0x0 |
Normal operating range |
|
[06:06] RO |
PCIE_CAP_SEL_DEEMPHASIS
Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. For more information, see section 4.2.6 of PCI Express Base Specification. When the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.
This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _3_5_DB |
0x1 |
-3.5 dB |
| _6_DB |
0x0 |
-6 dB |
|
[05:05] RW |
PCIE_CAP_HW_AUTO_SPEED_DISABLE
Hardware Autonomous Speed Disable. When set, this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.
For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.
Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[04:04] RW/V |
PCIE_CAP_ENTER_COMPLIANCE
Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis bit) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link.
Default value of this bit following Fundamental Reset is 0b.
For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.
Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.
This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.
After the software requests entering Polling.Compliance by setting this Enter Compliance bit, software should request exiting from Polling.Compliance by clearing this Enter Compliance bit only after controller sends out Compliance Pattern.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[03:00] RW |
PCIE_CAP_TARGET_LINK_SPEED
Target Link Speed. For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired target Link speed. All encodings other than the defined encodings are reserved.
If a value is written to this field that does not correspond to a supported speed (as indicated by the Supported Link Speeds Vector), the result is undefined.
If either of the Enter Compliance or Enter Modified Compliance bits are implemented, then this field must also be implemented.
The default value of this field is the highest Link speed supported by the component (as reported in the Max Link Speed field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.
For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode.
For Upstream Ports, if the Enter Compliance bit is Clear, this field is permitted to have no effect.
For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.
Components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0000b.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x5;
| Valid Values |
| Name | Value(s) | Description |
| SUP_LINK_SPEED_VECTOR_BIT_0 |
0x1 |
Supported Link Speeds Vector field bit 0 |
| SUP_LINK_SPEED_VECTOR_BIT_1 |
0x2 |
Supported Link Speeds Vector field bit 1 |
| SUP_LINK_SPEED_VECTOR_BIT_2 |
0x3 |
Supported Link Speeds Vector field bit 2 |
| SUP_LINK_SPEED_VECTOR_BIT_3 |
0x4 |
Supported Link Speeds Vector field bit 3 |
| SUP_LINK_SPEED_VECTOR_BIT_4 |
0x5 |
Supported Link Speeds Vector field bit 4 |
| SUP_LINK_SPEED_VECTOR_BIT_5 |
0x6 |
Supported Link Speeds Vector field bit 5 |
| SUP_LINK_SPEED_VECTOR_BIT_6 |
0x7 |
Supported Link Speeds Vector field bit 6 |
|
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+0x000000b0 Register(32 bit) PCI_MSIX_CAP_ID_NEXT_CTRL_REG
MSI-X Capability ID, Next Pointer, Control Register.
This Register holds MSI-X Capability ID, Next Capability pointer. It also controls the MSI-X behaviour.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010000b0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00100011 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
| Name |
PCI_MSIX_ENABLE |
PCI_MSIX_FUNCTION_MASK |
RSVDP_27 |
PCI_MSIX_TABLE_SIZE |
PCI_MSIX_CAP_NEXT_OFFSET |
PCI_MSIX_CAP_ID |
| Access |
RW |
RW |
RO |
RO |
RO |
RO |
[31:31] RW |
PCI_MSIX_ENABLE
MSI-X Enable. If Set and the MSI Enable bit in the MSI Message Control Register for MSI is Clear, the Function is permitted to use MSI-X to request service and is prohibited from using INTx interrupts (if implemented). System configuration software Sets this bit to enable MSI-X. A device driver is prohibited from writing this bit to mask a Function's service request. If Clear, the Function is prohibited from using MSI-X to request service.
Reset: hex:0x0;
|
[30:30] RW |
PCI_MSIX_FUNCTION_MASK
Function Mask. If Set, all of the vectors associated with the Function are masked, regardless of their per-vector Mask bit values. If Clear, each vector's Mask bit determines whether the vector is masked or not. Setting or Clearing the MSI-X Function Mask bit has no effect on the value of the per-vector Mask bits.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[29:27] RO |
RSVDP_27
Reserved for future use.
Reset: hex:0x0;
|
[26:16] RO |
PCI_MSIX_TABLE_SIZE
MSI-X Table Size. System software reads this field to determine the MSI-X Table Size N, which is encoded as N-1. For example, a returned value of 000 0000 0011b indicates a table size of 4.
SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x010;
|
[15:08] RO |
PCI_MSIX_CAP_NEXT_OFFSET
MSI-X Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO |
PCI_MSIX_CAP_ID
MSI-X Capability ID. This field indicates the MSI-X Capability structure. This field must return a Capability ID of 11h indicating that this is an MSI-X Capability structure.
Reset: hex:0x11;
|
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+0x000000b4 Register(32 bit) MSIX_TABLE_OFFSET_REG
MSI-X Table Offset and BIR Register.
This register provides Table BIR and MSI-x Table offset select.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010000b4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000005 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
| Name |
PCI_MSIX_TABLE_OFFSET |
PCI_MSIX_BIR |
| Access |
RO |
RO |
[31:03] RO |
PCI_MSIX_TABLE_OFFSET
MSI-X Table Offset. Used as an offset from the address contained by one of the Function's Base Address Registers to point to the base of the MSI-X Table. The lower 3 Table BIR bits are masked off (set to zero) by software to form a 32-bit QWORD-aligned offset.
SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Offset" (PCI_MSIX_TABLE_OFFSET field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_OFFSET field in the PF MSIX_TABLE_OFFSET_REG register.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x00000000;
|
[02:00] RO |
PCI_MSIX_BIR
MSI-X Table BAR Indicator Register Field. This field indicates which one of a Function's Base Address Registers , located beginning at 10h in Configuration Space, or entry in the Enhanced Allocation capability with a matching BEI , is used to map the Function's MSI-X Table into Memory Space. All encodings other than the defined encodings are reserved. For a 64-bit Base Address Register , the Table BIR indicates the lower DWORD. For Functions with Type 1 Configuration Space headers, BIR values 2 through 5 are also Reserved.
SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table BAR Indicator Register" (PCI_MSIX_BIR field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_BIR field in the PF MSIX_TABLE_OFFSET_REG register.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x5;
| Valid Values |
| Name | Value(s) | Description |
| BAR_10 |
0x0 |
Base Address Register 10h |
| BAR_14 |
0x1 |
Base Address Register 14h |
| BAR_18 |
0x2 |
Base Address Register 18h |
| BAR_1C |
0x3 |
Base Address Register 1Ch |
| BAR_20 |
0x4 |
Base Address Register 20h |
| BAR_24 |
0x5 |
Base Address Register 24h |
|
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+0x000000b8 Register(32 bit) MSIX_PBA_OFFSET_REG
MSI-X PBA Offset and BIR Register.
This register provides PBA Offset and PBA BIR value.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010000b8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000805 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
| Name |
PCI_MSIX_PBA_OFFSET |
PCI_MSIX_PBA_BIR |
| Access |
RO |
RO |
[31:03] RO |
PCI_MSIX_PBA_OFFSET
MSI-X PBA Offset. Used as an offset from the address contained by one of the Function's Base Address Registers to point to the base of the MSI-X PBA. The lower 3 PBA BIR bits are masked off (set to zero) by software to form a 32-bit QWORD-aligned offset.
SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA Offset" (PCI_MSIX_PBA_OFFSET field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_OFFSET field in the PF MSIX_PBA_OFFSET_REG register.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x00000100;
|
[02:00] RO |
PCI_MSIX_PBA_BIR
MSI-X PBA BIR. This field indicates which one of a Function's Base Address Registers , located beginning at 10h in Configuration Space, or entry in the Enhanced Allocation capability with a matching BEI, is used to map the Function's MSI-X PBA into Memory Space. The PBA BIR value definitions are identical to those for the Table BIR .
SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA BIR" (PCI_MSIX_PBA_BIR field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_BIR field in the PF MSIX_PBA_OFFSET_REG register.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x5;
|
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+0x00000100 Register(32 bit) AER_EXT_CAP_HDR_OFF
Advanced Error Reporting Extended Capability Header.
Advanced Error Reporting Extended Capability Header provides information about Capability ID, Version, and next offset.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000100 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x14820001 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
| Name |
NEXT_OFFSET |
CAP_VERSION |
CAP_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x148;
|
[19:16] RO |
CAP_VERSION
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field must be 2h if the End-End TLP Prefix Supported bit is set and must be 1h or 2h otherwise.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x2;
|
[15:00] RO |
CAP_ID
AER Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. The Extended Capability ID for the Advanced Error Reporting Capability is 0001h.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0001;
|
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+0x00000104 Register(32 bit) UNCORR_ERR_STATUS_OFF
Uncorrectable Error Status Register.
The Uncorrectable Error Status Register (Offset 04h) indicates error detection status of individual errors on a PCI Express device Function.
An individual error status bit that is Set indicates that a particular error was detected; software may clear an error status by writing a 1b to the respective bit.
Register bits not implemented by the Function are hardwired to 0b.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000104 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x0d262030 |
|
|
Undefined |
0x0d200000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
- |
- |
0 |
- |
0 |
0 |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_31 |
PCRC_CHECK_FAILED_STATUS |
MISROUTED_IDE_TLP_STATUS |
IDE_CHECK_FAILED_STATUS |
- |
TLP_PRFX_BLOCKED_ERR_STATUS |
- |
RSVDP_23 |
INTERNAL_ERR_STATUS |
- |
UNSUPPORTED_REQ_ERR_STATUS |
ECRC_ERR_STATUS |
MALF_TLP_ERR_STATUS |
REC_OVERFLOW_ERR_STATUS |
UNEXP_CMPLT_ERR_STATUS |
CMPLT_ABORT_ERR_STATUS |
CMPLT_TIMEOUT_ERR_STATUS |
FC_PROTOCOL_ERR_STATUS |
POIS_TLP_ERR_STATUS |
RSVDP_6 |
SURPRISE_DOWN_ERR_STATUS |
DL_PROTOCOL_ERR_STATUS |
RSVDP_0 |
| Access |
RO |
RW/1C/V |
RW/1C/V |
RW/1C/V |
- |
RW/1C |
- |
RO |
RW/1C/V |
- |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RO |
RW/1C/V |
RW/1C/V |
RO |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:30] RW/1C/V |
PCRC_CHECK_FAILED_STATUS
PCRC Check Failed Status (optional). Status bit for PCRC Check Failed Status.
Note: This register field is sticky.
Reset: hex:0x0;
|
[29:29] RW/1C/V |
MISROUTED_IDE_TLP_STATUS
Misrouted IDE TLP Status (optional). Status bit for Misrouted IDE TLP Status.
Note: This register field is sticky.
Reset: hex:0x0;
|
[28:28] RW/1C/V |
IDE_CHECK_FAILED_STATUS
IDE Check Failed Status (optional). Status bit for IDE Check Failed Status.
Note: This register field is sticky.
Reset: hex:0x0;
|
[25:25] RW/1C |
TLP_PRFX_BLOCKED_ERR_STATUS
TLP Prefix Blocked Error Status. Status bit for TLP Prefix Blocked Error.
Note: Not supported.
Note: This register field is sticky.
Reset: hex:0x0;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:22] RW/1C/V |
INTERNAL_ERR_STATUS
Uncorrectable Internal Error Status. This field gives status of the Uncorrectable Internal Error.
The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more information, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.
This register field is reserved for VFs.
Note: This register field is sticky.
Reset: hex:0x0;
|
[20:20] RW/1C/V |
UNSUPPORTED_REQ_ERR_STATUS
Unsupported Request Error Status. This field represents status of Unsupported Request Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[19:19] RW/1C/V |
ECRC_ERR_STATUS
ECRC Error Status. This field represents status of ECRC Error.
Note:If CX_ECRC_ENABLE=0 the register field always reads 0.
Note: This register field is sticky.
Reset: hex:0x0;
|
[18:18] RW/1C/V |
MALF_TLP_ERR_STATUS
Malformed TLP Status. This field represents status of Malformed TLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[17:17] RW/1C/V |
REC_OVERFLOW_ERR_STATUS
Receiver Overflow Status. Status bit for Receiver Overflow.
Note: This register field is sticky.
Reset: hex:0x0;
|
[16:16] RW/1C/V |
UNEXP_CMPLT_ERR_STATUS
Unexpected Completion Status. Status bit for Unexpected Completion.
Note: This register field is sticky.
Reset: hex:0x0;
|
[15:15] RW/1C/V |
CMPLT_ABORT_ERR_STATUS
Completer Abort Status. Status bit for Completer Abort.
Note: This register field is sticky.
Reset: hex:0x0;
|
[14:14] RW/1C/V |
CMPLT_TIMEOUT_ERR_STATUS
Completion Timeout Status. Status for Completion Timeout.
Note: This register field is sticky.
Reset: hex:0x0;
|
[13:13] RW/1C/V |
FC_PROTOCOL_ERR_STATUS
Flow Control Protocol Error Status. Status bit for Flow Control Protocol Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[12:12] RW/1C/V |
POIS_TLP_ERR_STATUS
Poisoned TLP Status. Status bit for Poisoned TLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[11:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x00;
|
[05:05] RW/1C/V |
SURPRISE_DOWN_ERR_STATUS
Surprise Down Error Status (Optional). Status bit for Surprise Down Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[04:04] RW/1C/V |
DL_PROTOCOL_ERR_STATUS
Data Link Protocol Error Status. Status bit for Data Link Protocol Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[03:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x0;
|
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+0x00000108 Register(32 bit) UNCORR_ERR_MASK_OFF
Uncorrectable Error Mask Register.
The Uncorrectable Error Mask Register controls reporting of individual errors by the device Function to the PCI Express Root Complex through a PCI Express error Message.
A masked error (respective bit Set in the mask register) is not recorded or reported in the Header Log, TLP Prefix Log, or First Error Pointer, and is not reported to the PCI Express Root Complex by this Function.
There is a mask bit per error bit of the Uncorrectable Error Status register. Register fields for bits not implemented by the Function are hardwired to 0b.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000108 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00400000 |
|
|
Unaffected |
0x00200000 |
|
|
Undefined |
0x00200000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_31 |
PCRC_CHECK_FAILED_MASK |
MISROUTED_IDE_TLP_MASK |
IDE_CHECK_FAILED_MASK |
DMWR_EGRESS_BLOCKED_ERR_MASK |
RSVDP_26 |
TLP_PRFX_BLOCKED_ERR_MASK |
ATOMIC_EGRESS_BLOCKED_ERR_MASK |
RSVDP_23 |
INTERNAL_ERR_MASK |
- |
UNSUPPORTED_REQ_ERR_MASK |
ECRC_ERR_MASK |
MALF_TLP_ERR_MASK |
REC_OVERFLOW_ERR_MASK |
UNEXP_CMPLT_ERR_MASK |
CMPLT_ABORT_ERR_MASK |
CMPLT_TIMEOUT_ERR_MASK |
FC_PROTOCOL_ERR_MASK |
POIS_TLP_ERR_MASK |
RSVDP_6 |
SURPRISE_DOWN_ERR_MASK |
DL_PROTOCOL_ERR_MASK |
RSVDP_0 |
| Access |
RO |
RW |
RW |
RW |
RO |
RO |
RO |
RO |
RO |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RO |
RO |
RW |
RO |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:30] RW |
PCRC_CHECK_FAILED_MASK
PCRC Check Failed Mask (optional)
Note: This register field is sticky.
Reset: hex:0x0;
|
[29:29] RW |
MISROUTED_IDE_TLP_MASK
Misrouted IDE TLP Mask (optional)
Note: This register field is sticky.
Reset: hex:0x0;
|
[28:28] RW |
IDE_CHECK_FAILED_MASK
IDE Check Failed Mask (optional)
Note: This register field is sticky.
Reset: hex:0x0;
|
[27:27] RO |
DMWR_EGRESS_BLOCKED_ERR_MASK
Deferrable Memory Write Egress Block Mask (Optional). Mask bit for Deferrable Memory Write Egress Block Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[26:26] RO |
RSVDP_26
Reserved for future use.
Reset: hex:0x0;
|
[25:25] RO |
TLP_PRFX_BLOCKED_ERR_MASK
TLP Prefix Blocked Error Mask. Mask bit for TLP Prefix Blocked Error.
Note: Not supported.
Note: This register field is sticky.
Reset: hex:0x0;
|
[24:24] RO |
ATOMIC_EGRESS_BLOCKED_ERR_MASK
AtomicOp Egress Block Mask (Optional). Mask bit for AtomicOp Egress Block Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:22] RW |
INTERNAL_ERR_MASK
Uncorrectable Internal Error Mask (Optional). Mask bit for Uncorrectable Internal Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[20:20] RW |
UNSUPPORTED_REQ_ERR_MASK
Unsupported Request Error Mask. Mask bit for Unsupported Request Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[19:19] RW |
ECRC_ERR_MASK
ECRC Error Mask (Optional). Mask bit for ECRC Error.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[18:18] RW |
MALF_TLP_ERR_MASK
Malformed TLP Mask. Mask bit for Malformed TLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[17:17] RW |
REC_OVERFLOW_ERR_MASK
Receiver Overflow Mask (Optional). This field represents Receiver Overflow Mask.
Note: This register field is sticky.
Reset: hex:0x0;
|
[16:16] RW |
UNEXP_CMPLT_ERR_MASK
Unexpected Completion Mask. Mask bit for Unexpected Completion Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[15:15] RW |
CMPLT_ABORT_ERR_MASK
Completer Abort Error Mask (Optional). Mask bit for Completer Abort Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[14:14] RW |
CMPLT_TIMEOUT_ERR_MASK
Completion Timeout Error Mask. Mask bit for Completion Timeout Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[13:13] RW |
FC_PROTOCOL_ERR_MASK
Flow Control Protocol Error Mask. Mask bit for Flow Control Protocol Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[12:12] RW |
POIS_TLP_ERR_MASK
Poisoned TLP Error Mask. Mask bit for Poisoned TLP Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[11:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x00;
|
[05:05] RO |
SURPRISE_DOWN_ERR_MASK
Surprise Down Error Mask. Mask bit for Surprise Down Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[04:04] RW |
DL_PROTOCOL_ERR_MASK
Data Link Protocol Error Mask. This field informs whether Data Link Protocol Error is masked or not.
Note: This register field is sticky.
Reset: hex:0x0;
|
[03:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x0;
|
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+0x0000010c Register(32 bit) UNCORR_ERR_SEV_OFF
Uncorrectable Error Severity Register.
The Uncorrectable Error Severity Register controls whether an individual error is reported as a Non-fatal or Fatal error.
An error is reported as fatal when the corresponding error bit in the severity register is Set. If the bit is Clear, the corresponding error is considered non-fatal.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100010c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x10462030 |
|
|
Unaffected |
0x05200000 |
|
|
Undefined |
0x05200000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
0 |
- |
0 |
- |
0 |
1 |
- |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_31 |
PCRC_CHECK_FAILED_SEV |
MISROUTED_IDE_TLP_SEV |
IDE_CHECK_FAILED_SEV |
DMWR_EGRESS_BLOCKED_ERR_SEVERITY |
- |
TLP_PRFX_BLOCKED_ERR_SEVERITY |
- |
RSVDP_23 |
INTERNAL_ERR_SEVERITY |
- |
UNSUPPORTED_REQ_ERR_SEVERITY |
ECRC_ERR_SEVERITY |
MALF_TLP_ERR_SEVERITY |
REC_OVERFLOW_ERR_SEVERITY |
UNEXP_CMPLT_ERR_SEVERITY |
CMPLT_ABORT_ERR_SEVERITY |
CMPLT_TIMEOUT_ERR_SEVERITY |
FC_PROTOCOL_ERR_SEVERITY |
POIS_TLP_ERR_SEVERITY |
RSVDP_6 |
SURPRISE_DOWN_ERR_SVRITY |
DL_PROTOCOL_ERR_SEVERITY |
RSVDP_0 |
| Access |
RO |
RW |
RW |
RW |
RO |
- |
RO |
- |
RO |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RO |
RO |
RW |
RO |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:30] RW |
PCRC_CHECK_FAILED_SEV
PCRC Check Failed Severity (optional)
Note: This register field is sticky.
Reset: hex:0x0;
|
[29:29] RW |
MISROUTED_IDE_TLP_SEV
Misrouted IDE TLP Severity (optional)
Note: This register field is sticky.
Reset: hex:0x0;
|
[28:28] RW |
IDE_CHECK_FAILED_SEV
IDE Check Failed Severity (optional)
Note: This register field is sticky.
Reset: hex:0x1;
|
[27:27] RO |
DMWR_EGRESS_BLOCKED_ERR_SEVERITY
Deferrable Memory Write Egress Blocked Severity (Optional). Severity bit for Deferrable Memory Write Egress Blocked Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[25:25] RO |
TLP_PRFX_BLOCKED_ERR_SEVERITY
TLP Prefix Blocked Error Severity (Optional). Severity bit for TLP Prefix Blocked Error.
Note: Not supported.
Note: This register field is sticky.
Reset: hex:0x0;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:22] RW |
INTERNAL_ERR_SEVERITY
Uncorrectable Internal Error Severity (Optional). Severity bit for Uncorrectable Internal Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[20:20] RW |
UNSUPPORTED_REQ_ERR_SEVERITY
Unsupported Request Error Severity. Severity bit for Unsupported Request Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[19:19] RW |
ECRC_ERR_SEVERITY
ECRC Error Severity (Optional). Severity bit for ECRC Error.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[18:18] RW |
MALF_TLP_ERR_SEVERITY
Malformed TLP Severity. Severity bit for Malformed TLP.
Note: This register field is sticky.
Reset: hex:0x1;
|
[17:17] RW |
REC_OVERFLOW_ERR_SEVERITY
Receiver Overflow Error Severity (Optional). Severity bit for Receiver Overflow Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[16:16] RW |
UNEXP_CMPLT_ERR_SEVERITY
Unexpected Completion Error Severity. Severity bit for Unexpected Completion Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[15:15] RW |
CMPLT_ABORT_ERR_SEVERITY
Completer Abort Error Severity (Optional). Severity bit for Completer Abort Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[14:14] RW |
CMPLT_TIMEOUT_ERR_SEVERITY
Completion Timeout Error Severity. Severity bit for Completion Timeout Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[13:13] RW |
FC_PROTOCOL_ERR_SEVERITY
Flow Control Protocol Error Severity (Optional). Severity bit for Flow Control Protocol Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[12:12] RW |
POIS_TLP_ERR_SEVERITY
Poisoned TLP Severity. Severity bit for Poisoned TLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[11:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x00;
|
[05:05] RO |
SURPRISE_DOWN_ERR_SVRITY
Surprise Down Error Severity (Optional). Severity bit for Surprise Down Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[04:04] RW |
DL_PROTOCOL_ERR_SEVERITY
Data Link Protocol Error Severity. Severity bit for Data Link Protocol Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[03:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x0;
|
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+0x00000110 Register(32 bit) CORR_ERR_STATUS_OFF
Correctable Error Status Register.
The Correctable Error Status register reports error status of individual correctable error sources on a PCI Express device Function.
When an individual error status bit is Set, it indicates that a particular error occurred; software may clear an error status by writing a 1b to the respective bit.
Register bits not implemented by the Function are hardwired to 0b by the controller.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000110 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_16 |
HEADER_LOG_OVERFLOW_STATUS |
CORRECTED_INT_ERR_STATUS |
ADVISORY_NON_FATAL_ERR_STATUS |
RPL_TIMER_TIMEOUT_STATUS |
RSVDP_9 |
REPLAY_NO_ROLEOVER_STATUS |
BAD_DLLP_STATUS |
BAD_TLP_STATUS |
RSVDP_1 |
RX_ERR_STATUS |
| Access |
RO |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RO |
RW/1C/V |
RW/1C/V |
RW/1C/V |
RO |
RW/1C/V |
[31:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0000;
|
[15:15] RW/1C/V |
HEADER_LOG_OVERFLOW_STATUS
Header Log Overflow Error Status (Optional). This field provides status of Header Log Overflow Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[14:14] RW/1C/V |
CORRECTED_INT_ERR_STATUS
Corrected Internal Error Status (Optional). This field provides status of Corrected Internal Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[13:13] RW/1C/V |
ADVISORY_NON_FATAL_ERR_STATUS
Advisory Non-Fatal Error Status. Status bit for Advisory Non-Fatal Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
[12:12] RW/1C/V |
RPL_TIMER_TIMEOUT_STATUS
Replay Timer Timeout Status. Status bit for Replay Timer Timeout.
Note: This register field is sticky.
Reset: hex:0x0;
|
[11:09] RO |
RSVDP_9
Reserved for future use.
Reset: hex:0x0;
|
[08:08] RW/1C/V |
REPLAY_NO_ROLEOVER_STATUS
REPLAY_NUM Rollover Status. Status bit for REPLAY_NUM Rollover.
Note: This register field is sticky.
Reset: hex:0x0;
|
[07:07] RW/1C/V |
BAD_DLLP_STATUS
Bad DLLP Status. Status bit for Bad DLLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[06:06] RW/1C/V |
BAD_TLP_STATUS
Bad TLP Status. Status bit for Bad TLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[05:01] RO |
RSVDP_1
Reserved for future use.
Reset: hex:0x00;
|
[00:00] RW/1C/V |
RX_ERR_STATUS
Receiver Error Status (Optional). This field provides status of Receiver Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x00000114 Register(32 bit) CORR_ERR_MASK_OFF
Correctable Error Mask Register.
The Correctable Error Mask Register controls reporting of individual correctable errors by this Function to the PCI Express Root Complex through a PCI Express error Message.
A masked error (respective bit Set in the mask register) is not reported to the PCI Express Root Complex by this Function.
There is a mask bit per error bit in the Correctable Error Status register. Register fields for bits not implemented by the Function are hardwired to 0b by the controller.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000114 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000e000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_16 |
HEADER_LOG_OVERFLOW_MASK |
CORRECTED_INT_ERR_MASK |
ADVISORY_NON_FATAL_ERR_MASK |
RPL_TIMER_TIMEOUT_MASK |
RSVDP_9 |
REPLAY_NO_ROLEOVER_MASK |
BAD_DLLP_MASK |
BAD_TLP_MASK |
RSVDP_1 |
RX_ERR_MASK |
| Access |
RO |
RW |
RW |
RW |
RW |
RO |
RW |
RW |
RW |
RO |
RW |
[31:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0000;
|
[15:15] RW |
HEADER_LOG_OVERFLOW_MASK
Header Log Overflow Error Mask (Optional). Masking bit for Header Log Overflow Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[14:14] RW |
CORRECTED_INT_ERR_MASK
Corrected Internal Error Mask (Optional). Masking bit for Corrected Internal Error Mask.
Note: This register field is sticky.
Reset: hex:0x1;
|
[13:13] RW |
ADVISORY_NON_FATAL_ERR_MASK
Advisory Non-Fatal Error Mask. Masking bit for Advisory Non-Fatal Error.
Note: This register field is sticky.
Reset: hex:0x1;
|
[12:12] RW |
RPL_TIMER_TIMEOUT_MASK
Replay Timer Timeout Mask. Masking bit for Replay Timer Timeout.
Note: This register field is sticky.
Reset: hex:0x0;
|
[11:09] RO |
RSVDP_9
Reserved for future use.
Reset: hex:0x0;
|
[08:08] RW |
REPLAY_NO_ROLEOVER_MASK
REPLAY_NUM Rollover Mask. Masking bit for REPLAY_NUM Rollover.
Note: This register field is sticky.
Reset: hex:0x0;
|
[07:07] RW |
BAD_DLLP_MASK
Bad DLLP Mask. Masking bit for Bad DLLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[06:06] RW |
BAD_TLP_MASK
Bad TLP Mask. Masking bit for Bad TLP.
Note: This register field is sticky.
Reset: hex:0x0;
|
[05:01] RO |
RSVDP_1
Reserved for future use.
Reset: hex:0x00;
|
[00:00] RW |
RX_ERR_MASK
Receiver Error Mask (Optional). Masking bit for Receiver Error.
Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x00000118 Register(32 bit) ADV_ERR_CAP_CTRL_OFF
Advanced Error Capabilities and Control Register.
Advanced Error Capabilities and Control Register provides information whether the individual capability is supported or not. If the capability is supported then it is enabled or not.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000118 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x000000a0 |
|
|
Unaffected |
0x00ffe000 |
|
|
Undefined |
0x00ffe000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_24 |
- |
CTO_PRFX_HDR_LOG_CAP |
TLP_PRFX_LOG_PRESENT |
MULTIPLE_HEADER_EN |
MULTIPLE_HEADER_CAP |
ECRC_CHECK_EN |
ECRC_CHECK_CAP |
ECRC_GEN_EN |
ECRC_GEN_CAP |
FIRST_ERR_POINTER |
| Access |
RO |
- |
RO |
RO/V |
RO |
RO |
RW |
RO |
RW |
RO |
RO/V |
[31:24] RO |
RSVDP_24
Reserved for future use.
Reset: hex:0x00;
|
[12:12] RO |
CTO_PRFX_HDR_LOG_CAP
Completion Timeout Prefix/Header Log Capable. If Set, this bit indicates that the Function records the prefix/header of Request TLPs that experience a Completion Timeout error.
Reset: hex:0x0;
|
[11:11] RO/V |
TLP_PRFX_LOG_PRESENT
TLP Prefix Log Present. If Set and the First Error Pointer is valid, indicates that the TLP Prefix Log register contains valid information. If Clear or if First Error Pointer is invalid, the TLP Prefix Log register is undefined. Default value of this bit is 0. This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear.
Note: This register field is sticky.
Reset: hex:0x0;
|
[10:10] RO |
MULTIPLE_HEADER_EN
Multiple Header Recording Enable. When Set, this bit enables the Function to record more than one error header. Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b. Default value of this bit is 0b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[09:09] RO |
MULTIPLE_HEADER_CAP
Multiple Header Recording Capable. If Set, this bit indicates that the Function is capable of recording more than one error header.
Note: This register field is sticky.
Reset: hex:0x0;
|
[08:08] RW |
ECRC_CHECK_EN
ECRC Check Enable. When Set, ECRC checking is enabled. Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b. Default value of this bit is 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[07:07] RO |
ECRC_CHECK_CAP
ECRC Check Capable. If Set, this bit indicates that the Function is capable of checking ECRC.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
|
[06:06] RW |
ECRC_GEN_EN
ECRC Generation Enable. When Set, ECRC generation is enabled. Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b. Default value of this bit is 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[05:05] RO |
ECRC_GEN_CAP
ECRC Generation Capable. If Set, this bit indicates that the Function is capable of generating ECRC.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
|
[04:00] RO/V |
FIRST_ERR_POINTER
First Error Pointer. The First Error Pointer is a field that identifies the bit position of the first error reported in the Uncorrectable Error Status register.
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x0000011c Register(32 bit) HDR_LOG_0_OFF
Header Log Register 0.
The Header Log Register 0 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 0, byte 1 of the header is in byte 2 of the Header Log Register 0, and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100011c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
FIRST_DWORD_FOURTH_BYTE |
FIRST_DWORD_THIRD_BYTE |
FIRST_DWORD_SECOND_BYTE |
FIRST_DWORD_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
FIRST_DWORD_FOURTH_BYTE
Byte 3 of Header log register of First 32-bit Data Word. This field represents fourth byte of First DW of Header. This field maps to:
HDR_LOG_0_OFF[31:24] = app_hdr_valid? app_hdr_log[7:0] : radm_hdr_log[7:0].
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
FIRST_DWORD_THIRD_BYTE
Byte 2 of Header log register of First 32-bit Data Word. This field represents third byte of First DW of Header. This field maps to:
HDR_LOG_0_OFF[23:16] = app_hdr_valid? app_hdr_log[15:8] : radm_hdr_log[15:8].
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
FIRST_DWORD_SECOND_BYTE
Byte 1 of Header log register of First 32-bit Data Word. This field represents second byte of First DW of Header. This field maps to:
HDR_LOG_0_OFF[15:8] = app_hdr_valid? app_hdr_log[23:16] : radm_hdr_log[23:16].
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
FIRST_DWORD_FIRST_BYTE
Byte 0 of Header log register of First 32-bit Data Word. This field represents first byte of First DW of Header. This field maps to:
HDR_LOG_0_OFF[7:0] = app_hdr_valid? app_hdr_log[31:24] : radm_hdr_log[31:24].
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x00000120 Register(32 bit) HDR_LOG_1_OFF
Header Log Register 1.
The Header Log Register 1 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 1, byte 1 of the header is in byte 2 of the Header Log Register 1 and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000120 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SECOND_DWORD_FOURTH_BYTE |
SECOND_DWORD_THIRD_BYTE |
SECOND_DWORD_SECOND_BYTE |
SECOND_DWORD_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
SECOND_DWORD_FOURTH_BYTE
Byte 3 of Header log register of Second 32-bit Data Word. This field represents fourth byte of Second DW of Header. This field maps to:
HDR_LOG_1_OFF[31:24] = app_hdr_valid? app_hdr_log[39:32] : radm_hdr_log[39:32].
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
SECOND_DWORD_THIRD_BYTE
Byte 2 of Header log register of Second 32-bit Data Word. This field represents third byte of Second DW of Header. This field maps to:
HDR_LOG_1_OFF[23:16] = app_hdr_valid? app_hdr_log[47:40] : radm_hdr_log[47:40].
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
SECOND_DWORD_SECOND_BYTE
Byte 1 of Header log register of Second 32-bit Data Word. This field represents second byte of Second DW of Header. This field maps to:
HDR_LOG_1_OFF[15:8] = app_hdr_valid? app_hdr_log[55:48] : radm_hdr_log[55:48].
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
SECOND_DWORD_FIRST_BYTE
Byte 0 of Header log register of Second 32-bit Data Word. This field represents first byte of Second DW of Header. This field maps to:
HDR_LOG_1_OFF[7:0] = app_hdr_valid? app_hdr_log[63:56] : radm_hdr_log[63:56].
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x00000124 Register(32 bit) HDR_LOG_2_OFF
Header Log Register 2.
The Header Log Register 2 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 2, byte 1 of the header is in byte 2 of the Header Log Register 2 and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000124 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
THIRD_DWORD_FOURTH_BYTE |
THIRD_DWORD_THIRD_BYTE |
THIRD_DWORD_SECOND_BYTE |
THIRD_DWORD_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
THIRD_DWORD_FOURTH_BYTE
Byte 3 of Header log register of Third 32-bit Data Word. This field represents fourth byte of Third DW of Header. This field maps to:
HDR_LOG_2_OFF[31:24] = app_hdr_valid? app_hdr_log[71:64] : radm_hdr_log[71:64].
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
THIRD_DWORD_THIRD_BYTE
Byte 2 of Header log register of Third 32-bit Data Word. This field represents third byte of Third DW of Header. This field maps to:
HDR_LOG_2_OFF[23:16] = app_hdr_valid? app_hdr_log[79:72] : radm_hdr_log[79:72].
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
THIRD_DWORD_SECOND_BYTE
Byte 1 of Header log register of Third 32-bit Data Word. This field represents second byte of Third DW of Header. This field maps to:
HDR_LOG_2_OFF[15:8] = app_hdr_valid? app_hdr_log[87:80] : radm_hdr_log[87:80].
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
THIRD_DWORD_FIRST_BYTE
Byte 0 of Header log register of Third 32-bit Data Word. This field represents first byte of Third DW of Header. This field maps to:
HDR_LOG_2_OFF[7:0] = app_hdr_valid? app_hdr_log[95:88] : radm_hdr_log[95:88].
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x00000128 Register(32 bit) HDR_LOG_3_OFF
Header Log Register 3.
The Header Log Register 3 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 3, byte 1 of the header is in byte 2 of the Header Log Register 3 and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000128 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
FOURTH_DWORD_FOURTH_BYTE |
FOURTH_DWORD_THIRD_BYTE |
FOURTH_DWORD_SECOND_BYTE |
FOURTH_DWORD_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
FOURTH_DWORD_FOURTH_BYTE
Byte 3 of Header log register of Fourth 32-bit Data Word. This field represents fourth byte of Fourth DW of Header. This field maps to:
HDR_LOG_3_OFF[31:24] = app_hdr_valid? app_hdr_log[103:96] : radm_hdr_log[103:96].
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
FOURTH_DWORD_THIRD_BYTE
Byte 2 of Header log register of Fourth 32-bit Data Word. This field represents third byte of Fourth DW of Header. This field maps to:
HDR_LOG_3_OFF[23:16] = app_hdr_valid? app_hdr_log[111:104] : radm_hdr_log[111:104].
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
FOURTH_DWORD_SECOND_BYTE
Byte 1 of Header log register of Fourth 32-bit Data Word. This field represents second byte of Fourth DW of Header. This field maps to:
HDR_LOG_3_OFF[15:8] = app_hdr_valid? app_hdr_log[119:112] : radm_hdr_log[119:112].
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
FOURTH_DWORD_FIRST_BYTE
Byte 0 of Header log register of Fourth 32-bit Data Word. This field represents first byte of Fourth DW of Header. This field maps to:
HDR_LOG_3_OFF[7:0] = app_hdr_valid? app_hdr_log[127:120] : radm_hdr_log[127:120].
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x00000138 Register(32 bit) TLP_PREFIX_LOG_1_OFF
TLP Prefix Log Register 1.
The First TLP Prefix Log Register contains the first End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000138 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CFG_TLP_PFX_LOG_1_FOURTH_BYTE |
CFG_TLP_PFX_LOG_1_THIRD_BYTE |
CFG_TLP_PFX_LOG_1_SECOND_BYTE |
CFG_TLP_PFX_LOG_1_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
CFG_TLP_PFX_LOG_1_FOURTH_BYTE
Byte 3 of Error TLP Prefix Log 1. This field contains fourth byte of First DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
CFG_TLP_PFX_LOG_1_THIRD_BYTE
Byte 2 of Error TLP Prefix Log 1. This field contains third byte of First DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
CFG_TLP_PFX_LOG_1_SECOND_BYTE
Byte 1 of Error TLP Prefix Log 1. This field contains second byte of First DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
CFG_TLP_PFX_LOG_1_FIRST_BYTE
Byte 0 of Error TLP Prefix Log 1. This field contains first byte of First DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x0000013c Register(32 bit) TLP_PREFIX_LOG_2_OFF
TLP Prefix Log Register 2.
The Second TLP Prefix Log Register contains the second End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100013c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CFG_TLP_PFX_LOG_2_FOURTH_BYTE |
CFG_TLP_PFX_LOG_2_THIRD_BYTE |
CFG_TLP_PFX_LOG_2_SECOND_BYTE |
CFG_TLP_PFX_LOG_2_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
CFG_TLP_PFX_LOG_2_FOURTH_BYTE
Byte 3 Error TLP Prefix Log 2. This field contains fourth byte of Second DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
CFG_TLP_PFX_LOG_2_THIRD_BYTE
Byte 2 Error TLP Prefix Log 2. This field contains third byte of Second DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
CFG_TLP_PFX_LOG_2_SECOND_BYTE
Byte 1 Error TLP Prefix Log 2. This field contains second byte of Second DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
CFG_TLP_PFX_LOG_2_FIRST_BYTE
Byte 0 Error TLP Prefix Log 2. This field contains first byte of Second DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x00000140 Register(32 bit) TLP_PREFIX_LOG_3_OFF
TLP Prefix Log Register 3.
The Third TLP Prefix Log Register contains the third End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000140 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CFG_TLP_PFX_LOG_3_FOURTH_BYTE |
CFG_TLP_PFX_LOG_3_THIRD_BYTE |
CFG_TLP_PFX_LOG_3_SECOND_BYTE |
CFG_TLP_PFX_LOG_3_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
CFG_TLP_PFX_LOG_3_FOURTH_BYTE
Byte 3 Error TLP Prefix Log 3. This field contains fourth byte of Third DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
CFG_TLP_PFX_LOG_3_THIRD_BYTE
Byte 2 Error TLP Prefix Log 3. This field contains third byte of Third DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
CFG_TLP_PFX_LOG_3_SECOND_BYTE
Byte 1 Error TLP Prefix Log 3. This field contains second byte of Third DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
CFG_TLP_PFX_LOG_3_FIRST_BYTE
Byte 0 Error TLP Prefix Log 3. This field contains first byte of Third DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
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+0x00000144 Register(32 bit) TLP_PREFIX_LOG_4_OFF
TLP Prefix Log Register 4.
The Fourth TLP Prefix Log Register contains the fourth End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000144 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CFG_TLP_PFX_LOG_4_FOURTH_BYTE |
CFG_TLP_PFX_LOG_4_THIRD_BYTE |
CFG_TLP_PFX_LOG_4_SECOND_BYTE |
CFG_TLP_PFX_LOG_4_FIRST_BYTE |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
CFG_TLP_PFX_LOG_4_FOURTH_BYTE
Byte 3 Error TLP Prefix Log 4. This field contains fourth byte of Fourth DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:16] RO/V |
CFG_TLP_PFX_LOG_4_THIRD_BYTE
Byte 2 Error TLP Prefix Log 4. This field contains third byte of Fourth DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:08] RO/V |
CFG_TLP_PFX_LOG_4_SECOND_BYTE
Byte 1 Error TLP Prefix Log 4. This field contains second byte of Fourth DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:00] RO/V |
CFG_TLP_PFX_LOG_4_FIRST_BYTE
Byte 0 Error TLP Prefix Log 4. This field contains first byte of Fourth DW of TLP Prefix.
Note: This register field is sticky.
Reset: hex:0x00;
|
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+0x00000148 Register(32 bit) SPCIE_CAP_HEADER_REG
SPCIE Capability Header.
This Register provides Capability Id, Capability Version, and next Offset of SPCIE Structure.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000148 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x15810019 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
| Name |
NEXT_OFFSET |
CAP_VERSION |
EXTENDED_CAP_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of Capabilities.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x158;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0fff |
Max value. |
| MIN_VAL |
0x0 |
Min value |
|
[19:16] RO |
CAP_VERSION
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x0f |
Max value |
|
[15:00] RO |
EXTENDED_CAP_ID
Secondary PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. PCI Express Extended Capability ID for the Secondary PCI Express Extended Capability is 0019h.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0019;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffff |
Max value |
| MIN_VAL |
0x0 |
Min value |
|
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+0x0000014c Register(32 bit) LINK_CONTROL3_REG
Link Control 3 Register.
This Register controls equilization and equilization interrupt.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100014c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000000 |
|
|
Unaffected |
0x00000001 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_2 |
EQ_REQ_INT_EN |
PERFORM_EQ |
| Access |
RO |
RO |
RO/V |
[31:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x00000000;
|
[01:01] RO |
EQ_REQ_INT_EN
Link Equalization Request Interrupt Enable. This bit is RW for Downstream Ports and for Upstream Ports when Crosslink Supported is 1b. This bit is not applicable and is RsvdP for Upstream Ports when the Crosslink Supported bit is 0b. If the Port does not support 8.0 GT/s, this bit is permitted to be hardwired to 0b by the controller.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When Set, this bit enables the generation of an interrupt to indicate that the Link Equalization Request 8.0 GT/s bit, the Link Equalization Request 16.0 GT/s bit, or the Link Equalization Request 32.0 GT/s bit has been set. |
| CLEAR |
0x0 |
Clear |
|
[00:00] RO/V |
PERFORM_EQ
Perform Equalization. This bit is RW for Downstream Ports and for Upstream Ports when Crosslink Supported is 1b. This bit is not applicable and is RsvdP for Upstream Ports when the Crosslink Supported bit is 0b. If the Port does not support 8.0 GT/s, this bit is permitted to be hardwired to 0b by the controller. If the Link is in Gen6 rate, setting this bit to 1b does not take effect because the Gen6 Base Spec says: All equalization procedures at the 64.0 GT/s data rate, including re-equalization, must be initiated from the 32.0 GT/s data rate only. If you want to perform Gen6 EQ, first you must change the Link to Gen5 data rate and then set the Target link Speed to Gen6, PERFORM_EQ to 1b and the Retrain Link bit to 1b in the Downstream Port.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is 1b and a 1b is written to the Retrain Link bit with the Target Link Speed field set to 8.0 GT/s or higher, the Downstream Port must perform Link Equalization. |
| CLEAR |
0x0 |
Clear |
|
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+0x00000150 Register(32 bit) LANE_ERR_STATUS_REG
Lane Error Status Register.
This Register contains Lane Error Status Bits per Lane.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000150 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_LANE_ERR_STATUS |
LANE_ERR_STATUS |
| Access |
RO |
RW/1C/V |
[31:02] RO |
RSVDP_LANE_ERR_STATUS
Reserved for future use.
Reset: hex:0x00000000;
|
[01:00] RW/1C/V |
LANE_ERR_STATUS
Lane Error Status Bits per Lane. Each bit indicates if the corresponding Lane detected a Lane-based error. A value of 1b indicates that a Lane based-error was detected on the corresponding Lane Number. For Ports that are narrower than 32 Lanes, the unused upper bits [31: Maximum Link Width] are RsvdZ. For Ports that do not support 8.0 GT/s and do not set these bits based on 8b/10b errors , this field is permitted to be hardwired to 0 by the controller.
Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x00000154 Register(32 bit) SPCIE_CAP_OFF_0CH_REG
Lane Equalization Control Register for lanes 1 and 0.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000154 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x74007400 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_31 |
USP_RX_PRESET_HINT1 |
USP_TX_PRESET1 |
RSVDP_23 |
DSP_RX_PRESET_HINT1 |
DSP_TX_PRESET1 |
RSVDP_15 |
USP_RX_PRESET_HINT0 |
USP_TX_PRESET0 |
RSVDP_7 |
DSP_RX_PRESET_HINT0 |
DSP_TX_PRESET0 |
| Access |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:28] RO |
USP_RX_PRESET_HINT1
Upstream Port 8.0 GT/s Receiver Preset Hint 1.
The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Field contains the Receiver preset hint 1 value sent or received during 8.0 GT/s Link Equalization. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field representss the value sent on Lane 0 during 8.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 0 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
Reset: hex:0x7;
|
[27:24] RO |
USP_TX_PRESET1
Upstream Port 8.0 GT/s Transmitter Preset 1.
The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Field contains the Transmitter preset 1 value sent or received during 8.0 GT/s Link Equalization. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field representss the value sent on Lane 0 during 8.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 0 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
Reset: hex:0x4;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:20] RO |
DSP_RX_PRESET_HINT1
Downstream Port 8.0 GT/s Receiver Preset Hint 1. Receiver preset hint 1 value that may be used as a suggested setting for 8.0 GT/s receiver equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP. Otherwise, this field is HwInit.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
|
[19:16] RO |
DSP_TX_PRESET1
Downstream Port 8.0 GT/s Transmitter Preset 1. Transmitter preset 1 value used for 8.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP. Otherwise, this field is HwInit.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
|
[15:15] RO |
RSVDP_15
Reserved for future use.
Reset: hex:0x0;
|
[14:12] RO |
USP_RX_PRESET_HINT0
Upstream Port 8.0 GT/s Receiver Preset Hint 0.
The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Field contains the Receiver preset hint 0 value sent or received during 8.0 GT/s Link Equalization. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field representss the value sent on Lane 0 during 8.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 0 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
Reset: hex:0x7;
|
[11:08] RO |
USP_TX_PRESET0
Upstream Port 8.0 GT/s Transmitter Preset 0.
The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Field contains the Transmitter preset 0 value sent or received during 8.0 GT/s Link Equalization. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field representss the value sent on Lane 0 during 8.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 0 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
Reset: hex:0x4;
|
[07:07] RO |
RSVDP_7
Reserved for future use.
Reset: hex:0x0;
|
[06:04] RO |
DSP_RX_PRESET_HINT0
Downstream Port 8.0 GT/s Receiver Preset Hint 0. Receiver preset hint 0 value that may be used as a suggested setting for 8.0 GT/s receiver equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP. Otherwise, this field is HwInit.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
|
[03:00] RO |
DSP_TX_PRESET0
Downstream Port 8.0 GT/s Transmitter Preset 0. Transmitter preset 0 value used for 8.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP. Otherwise, this field is HwInit.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
|
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+0x00000158 Register(32 bit) PL16G_EXT_CAP_HDR_REG
Physical Layer 16.0 GT/s Extended Capability Header.
Physical Layer 16.0 GT/s Extended Capability Header provides information about Capability ID, Version, and next offset.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000158 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x17c10026 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
| Name |
NEXT_OFFSET |
CAP_VERSION |
EXTENDED_CAP_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x17c;
|
[19:16] RO |
CAP_VERSION
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This bit depends on the version of the specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
|
[15:00] RO |
EXTENDED_CAP_ID
PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. The Extended Capability ID for the Physical Layer 16.0 GT/s Capability is 0026h.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0026;
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+0x0000015c Register(32 bit) PL16G_CAPABILITY_REG
16.0 GT/s Capabilities Register.
This register is reserved for the future update.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100015c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_0 |
| Access |
RO |
[31:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x00000000;
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+0x00000160 Register(32 bit) PL16G_CONTROL_REG
16.0 GT/s Control Register.
This register is reserved for the future update.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000160 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_0 |
| Access |
RO |
[31:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x00000000;
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+0x00000164 Register(32 bit) PL16G_STATUS_REG
16.0 GT/s Status Register.
16.0 GT/s Status Register provides status of equalization of 16.0 GT/s speed.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000164 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_5 |
LINK_EQ_16G_REQ |
EQ_16G_CPL_P3 |
EQ_16G_CPL_P2 |
EQ_16G_CPL_P1 |
EQ_16G_CPL |
| Access |
RO |
RW/1C/V |
RO/V |
RO/V |
RO/V |
RO/V |
[31:05] RO |
RSVDP_5
Reserved for future use.
Reset: hex:0x0000000;
|
[04:04] RW/1C/V |
LINK_EQ_16G_REQ
Link Equalization Request 16.0GT/s. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit is Set by hardware to request the 16.0 GT/s Link equalization process to be performed on the Link. |
| CLEAR |
0x0 |
Clear |
|
[03:03] RO/V |
EQ_16G_CPL_P3
Equalization 16.0GT/s Phase 3 Successful. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit indicates that Phase 3 of the 16.0 GT/s Transmitter Equalization procedure has successfully completed. |
| CLEAR |
0x0 |
Clear |
|
[02:02] RO/V |
EQ_16G_CPL_P2
Equalization 16.0GT/s Phase 2 Successful. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit indicates that Phase 2 of the 16.0 GT/s Transmitter Equalization procedure has successfully completed. |
| CLEAR |
0x0 |
Clear |
|
[01:01] RO/V |
EQ_16G_CPL_P1
Equalization 16.0GT/s Phase 1 Successful. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit indicates that Phase 1 of the 16.0 GT/s Transmitter Equalization procedure has successfully completed. |
| CLEAR |
0x0 |
Clear |
|
[00:00] RO/V |
EQ_16G_CPL
Equalization 16.0GT/s Complete. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
This bit indicates that the 16.0 GT/s Transmitter Equalization procedure has completed. |
| CLEAR |
0x0 |
Clear |
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+0x00000168 Register(32 bit) PL16G_LC_DPAR_STATUS_REG
16.0 GT/s Local Data Parity Mismatch Status Register.
The Local Data Parity Mismatch Status register is a 32-bit vector where each bit indicates if the local receiver detected a Data Parity mismatch on the Lane with the corresponding Lane number.
This Lane number is the default Lane number which is invariant to Link width and Lane reversal negotiation that occurs during Link training.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000168 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_LC_DPAR_STATUS |
LC_DPAR_STATUS |
| Access |
RO |
RW/1C/V |
[31:02] RO |
RSVDP_LC_DPAR_STATUS
Reserved for future use.
Reset: hex:0x00000000;
|
[01:00] RW/1C/V |
LC_DPAR_STATUS
Local Data Parity Mismatch Status. Each bit indicates if the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number. The default value of each bit is 0b. For Ports that are narrower than 32 Lanes, the unused upper bits [31: MaximumLink Width] are RsvdZ.
Reset: hex:0x0;
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+0x0000016c Register(32 bit) PL16G_FIRST_RETIMER_DPAR_STATUS_REG
16.0 GT/s First Retimer Data Parity Mismatch Status Register.
The First Retimer Data Parity Status register is a 32-bit vector where each bit indicates if the first Retimer of a Path detected a Data Parity mismatch on the Lane with the corresponding Lane number.
This Lane number is the default Lane number which is invariant to Link width and Lane reversal negotiation that occurs during Link training.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100016c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_FIRST_RETIMER_DPAR_STATUS |
FIRST_RETIMER_DPAR_STATUS |
| Access |
RO |
RW/1C/V |
[31:02] RO |
RSVDP_FIRST_RETIMER_DPAR_STATUS
Reserved for future use.
Reset: hex:0x00000000;
|
[01:00] RW/1C/V |
FIRST_RETIMER_DPAR_STATUS
First Retimer Data Parity Mismatch Status. Each bit indicates if the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number. The default value of each bit is 0b. The value of this field is undefined when no Retimers are present. For Ports that are narrower than 32 Lanes, the unused upper bits [31: Maximum Link Width] are RsvdZ.
Reset: hex:0x0;
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+0x00000170 Register(32 bit) PL16G_SECOND_RETIMER_DPAR_STATUS_REG
16.0 GT/s Second Retimer Data Parity Mismatch Status Register.
The Second Retimer Data Parity Status register is a 32-bit vector where each bit indicates if the second Retimer of a Path detected a Data Parity mismatch on the Lane with the corresponding Lane number.
This Lane number is the default Lane number which is invariant to Link width and Lane reversal negotiation that occurs during Link training.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000170 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_SECOND_RETIMER_DPAR_STATUS |
SECOND_RETIMER_DPAR_STATUS |
| Access |
RO |
RW/1C/V |
[31:02] RO |
RSVDP_SECOND_RETIMER_DPAR_STATUS
Reserved for future use.
Reset: hex:0x00000000;
|
[01:00] RW/1C/V |
SECOND_RETIMER_DPAR_STATUS
Second Retimer Data Parity Mismatch Status. Each bit indicates if the corresponding Lane detected a Data Parity mismatch. A value of 1b indicates that a mismatch was detected on the corresponding Lane Number. The default value of each bit is 0b. The value of this field is undefined when no Retimers are present or only one Retimer is present. For Ports that are narrower than 32 Lanes, the unused upper bits [31: Maximum Link Width] are RsvdZ.
Reset: hex:0x0;
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+0x00000178 Register(32 bit) PL16G_CAP_OFF_20H_REG
16.0 GT/s Lane Equalization Control Register for Lane 0-3.
This Equalization Control register consists of control fields required for Lane 0-3 16.0 GT/s equalization.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000178 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00004040 |
|
|
Unaffected |
0xffff0000 |
|
|
Undefined |
0xffff0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
USP_16G_TX_PRESET1 |
DSP_16G_TX_PRESET1 |
USP_16G_TX_PRESET0 |
DSP_16G_TX_PRESET0 |
| Access |
- |
RO |
RO |
RO |
RO |
[15:12] RO |
USP_16G_TX_PRESET1
Upstream Port 16.0 GT/s Transmitter Preset1. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field represents the value sent on Lane 1 during 16.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 1 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Case B also has a writable but not readable register internally with following access attributes. For case B and C, the writable register's value is set to implementation specific 16.0 GT/s Transmitter Preset bits in optional EQ TS2 OS if USP_SEND_8GT_EQ_TS2_DISABLE field of PORT_LOGIC - GEN3_RELATED_OFF register is 0b with RATE_SHADOW_SEL==01b.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x4;
|
[11:08] RO |
DSP_16G_TX_PRESET1
Downstream Port 16.0 GT/s Transmitter Preset1. Transmitter Preset of Lane 1 used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP. Otherwise, this field is HwInit.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
|
[07:04] RO |
USP_16G_TX_PRESET0
Upstream Port 16.0 GT/s Transmitter Preset0. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field represents the value sent on Lane 0 during 16.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 0 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Case B also has a writable but not readable register internally with following access attributes. For case B and C, the writable register's value is set to implementation specific 16.0 GT/s Transmitter Preset bits in optional EQ TS2 OS if USP_SEND_8GT_EQ_TS2_DISABLE field of PORT_LOGIC - GEN3_RELATED_OFF register is 0b with RATE_SHADOW_SEL==01b.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x4;
|
[03:00] RO |
DSP_16G_TX_PRESET0
Downstream Port 16.0 GT/s Transmitter Preset0. Transmitter Preset of Lane 0 used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP. Otherwise, this field is HwInit.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP
Reset: hex:0x0;
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+0x0000017c Register(32 bit) MARGIN_EXT_CAP_HDR_REG
Margining Extended Capability Header.
This register provides capbility ID, capability version and next offset value for Margining Extended Capability.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100017c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x18c10027 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
| Name |
NEXT_OFFSET |
CAP_VERSION |
EXTENDED_CAP_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greaterthan 0FFh.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x18c;
|
[19:16] RO |
CAP_VERSION
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
|
[15:00] RO |
EXTENDED_CAP_ID
PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. The Extended Capability ID for the Physical Layer 16.0 GT/s Margining Extended Capability is 0027h.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0027;
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+0x00000180 Register(32 bit) MARGIN_PORT_CAPABILITIES_STATUS_REG
Margining Port Capabilities and Status Register.
This register indicates the status of the Margining feature.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000180 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000000 |
|
|
Unaffected |
0x00030000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_18 |
MARGINING_SOFTWARE_READY |
MARGINING_READY |
RSVDP_1 |
MARGINING_USES_DRIVER_SOFTWARE |
| Access |
RO |
RO/V |
RO/V |
RO |
RO |
[31:18] RO |
RSVDP_18
Reserved for future use.
Reset: hex:0x0000;
|
[17:17] RO/V |
MARGINING_SOFTWARE_READY
Margining Software Ready. When Margining uses Driver Software is Set, then this bit, when Set, indicates that the required software has performed the required initialization. The value of this bit is undefined if Margining uses Driver Software is Clear. The default value of this bit is implementation specific. If Margining uses Driver Software is Clear, Margining Ready must be Set no later than 100 ms after the Link trains to 16.0 GT/s. Default value is implementation specific.
Reset: hex:0x0;
|
[16:16] RO/V |
MARGINING_READY
Margining Ready. Indicates when the Margining feature is ready to accept margining commands. Behavior is undefined if this bit is Clear and, for any Lane, any of the Receiver Number , Margin Type , Usage Model , or Margin Payload fields are written. If Margining uses Driver Software is Set, Margining Ready must be Set no later than 100 ms after the later of Margining Software Ready becoming Set or the link training to 16.0 GT/s.
Reset: hex:0x0;
|
[15:01] RO |
RSVDP_1
Reserved for future use.
Reset: hex:0x0000;
|
[00:00] RO |
MARGINING_USES_DRIVER_SOFTWARE
Margining uses Driver Software. If Set, indicates that Margining is partially implemented using Device Driver software. Margining Software Ready indicates when this software is initialized. If Clear, Margining does not require device driver software. In this case the value read from Margining Software Ready is undefined.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x00000184 Register(32 bit) MARGIN_LANE_CNTRL_STATUS0_REG
Margining Lane Control and Status Register for Lane 0.
The Margining Lane Control Register consists of control fields required for per-Lane margining.
The number of entries in this register are sized by Maximum Link Width.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000184 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00009c38 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
| Name |
MARGIN_PAYLOAD_STATUS |
RSVDP_23 |
USAGE_MODEL_STATUS |
MARGIN_TYPE_STATUS |
RECEIVER_NUMBER_STATUS |
MARGIN_PAYLOAD |
RSVDP_7 |
USAGE_MODEL |
MARGIN_TYPE |
RECEIVER_NUMBER |
| Access |
RO/V |
RO |
RO/V |
RO/V |
RO/V |
RW/V |
RO |
RW/V |
RW/V |
RW/V |
[31:24] RO/V |
MARGIN_PAYLOAD_STATUS
Margin Payload(Status) for Lane 0. This field is only meaningful, when the Margin Type is a defined encoding other than 'No Command'. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x00;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:22] RO/V |
USAGE_MODEL_STATUS
Usage Model(Status) for Lane 0. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[21:19] RO/V |
MARGIN_TYPE_STATUS
Margin Type(Status) for Lane 0. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[18:16] RO/V |
RECEIVER_NUMBER_STATUS
Receiver Number(Status) for Lane 0. For Downstream Ports, this field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[15:08] RW/V |
MARGIN_PAYLOAD
Margin Payload for Lane 0. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x9c;
|
[07:07] RO |
RSVDP_7
Reserved for future use.
Reset: hex:0x0;
|
[06:06] RW/V |
USAGE_MODEL
Usage Model for Lane 0. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[05:03] RW/V |
MARGIN_TYPE
Margin Type for Lane 0. The default value is 111b. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x7;
|
[02:00] RW/V |
RECEIVER_NUMBER
Receiver Number for Lane 0. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
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+0x00000188 Register(32 bit) MARGIN_LANE_CNTRL_STATUS1_REG
Margining Lane Control and Status Register for Lane 1.
The Margining Lane Control Register consists of control fields required for per-Lane margining.
The number of entries in this register are sized by Maximum Link Width.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000188 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00009c38 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
| Name |
MARGIN_PAYLOAD_STATUS |
RSVDP_23 |
USAGE_MODEL_STATUS |
MARGIN_TYPE_STATUS |
RECEIVER_NUMBER_STATUS |
MARGIN_PAYLOAD |
RSVDP_7 |
USAGE_MODEL |
MARGIN_TYPE |
RECEIVER_NUMBER |
| Access |
RO/V |
RO |
RO/V |
RO/V |
RO/V |
RW/V |
RO |
RW/V |
RW/V |
RW/V |
[31:24] RO/V |
MARGIN_PAYLOAD_STATUS
Margin Payload(Status) for Lane 1. This field is only meaningful, when the Margin Type is a defined encoding other than 'No Command'. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x00;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:22] RO/V |
USAGE_MODEL_STATUS
Usage Model(Status) for Lane 1. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[21:19] RO/V |
MARGIN_TYPE_STATUS
Margin Type(Status) for Lane 1. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[18:16] RO/V |
RECEIVER_NUMBER_STATUS
Receiver Number(Status) for Lane 1. For Downstream Ports, this field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[15:08] RW/V |
MARGIN_PAYLOAD
Margin Payload for Lane 1. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x9c;
|
[07:07] RO |
RSVDP_7
Reserved for future use.
Reset: hex:0x0;
|
[06:06] RW/V |
USAGE_MODEL
Usage Model for Lane 1. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
[05:03] RW/V |
MARGIN_TYPE
Margin Type for Lane 1. The default value is 111b. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x7;
|
[02:00] RW/V |
RECEIVER_NUMBER
Receiver Number for Lane 1. This field must be reset to the default value if the Port goes to DL_Down status.
Reset: hex:0x0;
|
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+0x0000018c Register(32 bit) PL32G_EXT_CAP_HDR_REG
Physical Layer 32.0 GT/s Extended Capability Header.
This register provides information about Capability ID, Version, and next offset.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100018c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x1b01002a |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
| Name |
NEXT_OFFSET |
CAP_VERSION |
EXTENDED_CAP_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1b0;
|
[19:16] RO |
CAP_VERSION
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This bit depends on the version of the specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
|
[15:00] RO |
EXTENDED_CAP_ID
PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. The Extended Capability ID for the Physical Layer 32.0 GT/s Capability is 002Ah.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x002a;
|
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+0x00000190 Register(32 bit) PL32G_CAPABILITY_REG
32.0 GT/s Capabilities Register.
This register provides Extended Capability of 32.0 GT/s Equalization.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000190 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000100 |
|
|
Unaffected |
0x00000400 |
|
|
Undefined |
0x00000400 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_16 |
MOD_TS_RSVD_USAGE_MODE |
- |
MOD_TS_TRAING_SET_MSG_SUPPORT |
MOD_TS_PCIE_SUPPORT |
RSVDP_2 |
NO_EQ_NEEDED_SUPPORT |
EQ_BYPASS_HIGHEST_RATE_SUPPORT |
| Access |
RO |
RO/V |
- |
RO/V |
RO |
RO |
RO |
RO |
[31:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0000;
|
[15:11] RO/V |
MOD_TS_RSVD_USAGE_MODE
Modified TS Reserved Usage Modes. Reserved bits for future Usage Modes defined by the PCISIG. Must be 0 0000b.
Reset: hex:0x00;
|
[09:09] RO/V |
MOD_TS_TRAING_SET_MSG_SUPPORT
Modified TS Usage Mode 1 Supported, Training Set Message.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates that this Port supports sending and recieving vendor specific Training Set Messages (Modified TS Usage 001b). |
|
[08:08] RO |
MOD_TS_PCIE_SUPPORT
Modified TS Usage Mode 0 Supported. This bit must be 1b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates that this Port supports PCI Express (Modified TS Usage 000b). |
|
[07:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x00;
|
[01:01] RO |
NO_EQ_NEEDED_SUPPORT
No Equalization Needed Support.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When Set, this Port supports controlling whether or not Equalization is needed. |
|
[00:00] RO |
EQ_BYPASS_HIGHEST_RATE_SUPPORT
Equalization bypass to highest rate Supported. Must be 1b for Ports that support 32.0 GT/s or higher data rates.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When Set, this Port supports controlling whether the Port negotiates to skip equalization for speeds other than the highest common supported speed. |
|
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+0x00000194 Register(32 bit) PL32G_CONTROL_REG
32.0 GT/s Control Register.
This register controls the 32.0 GT/s capabilities.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000194 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_11 |
MOD_TS_USAGE_MODE_SELECT |
RSVDP_2 |
NO_EQ_NEEDED_DISABLE |
EQ_BYPASS_HIGHEST_RATE_DISABLE |
| Access |
RO |
RO/V |
RO |
RW/V |
RW/V |
[31:11] RO |
RSVDP_11
Reserved for future use.
Reset: hex:0x000000;
|
[10:08] RO/V |
MOD_TS_USAGE_MODE_SELECT
Modified TS Usage Mode Selected. This field indicates which Usage Mode is used by this Downstream Port. In Upstream Ports, this field is RsvdP. Default is 000b. All encodings other than the defined encodings are reserved. Unused bits in this field are permitted to be hardwired to 0b. If the only supported usage mode is PCI Express, this field is permitted to he hardwired to 000b. If 001b, PCIe protocol only with vendor defined Training Set Messages. If 010b, Alternate Protocol Negotiation.
Reset: hex:0x0;
|
[07:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x00;
|
[01:01] RW/V |
NO_EQ_NEEDED_DISABLE
No Equalization Needed Disable. If No Equalization Needed Supported is Set, this bit is RWS with a default value of 0b.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
When Clear, this Port is permitted to indicate that it does not require equalization. When Set, this Port must always indicate that it requires equalization. |
|
[00:00] RW/V |
EQ_BYPASS_HIGHEST_RATE_DISABLE
Equalization bypass to highest rate Disable. If Equalization bypass to highest rate Supported is Set, this bit is RWS with a default value of 0b.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
When Clear, this Port indicates during Link Training that it wishes to train to the highest common link data rate and skip equalization of intermediate data rates. |
|
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+0x00000198 Register(32 bit) PL32G_STATUS_REG
32.0 GT/s Status Register.
This register provides information related to 32.0 GT/s equalization.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000198 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000200 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_11 |
NO_EQ_NEEDED_RCVD |
TX_PRECODE_REQ |
TX_PRECODING_ON |
RX_ENH_LINK_BEHAVIOR_CTRL |
MOD_TS_RCVD |
LINK_EQ_32G_REQ |
EQ_32G_CPL_P3 |
EQ_32G_CPL_P2 |
EQ_32G_CPL_P1 |
EQ_32G_CPL |
| Access |
RO |
RO/V |
RW/V |
RO/V |
RO/V |
RO/V |
RW/1C/V |
RO/V |
RO/V |
RO/V |
RO/V |
[31:11] RO |
RSVDP_11
Reserved for future use.
Reset: hex:0x000000;
|
[10:10] RO/V |
NO_EQ_NEEDED_RCVD
No Equalization Needed Received. This bit is Set when this Port either received a Modified TS1/TS2 with the No Equalization Needed bit Set or received a non-modified TS1/TS2 was received with the No Equalization Needed encoding. This bit is cleared on DL_Down.
Reset: hex:0x0;
|
[09:09] RW/V |
TX_PRECODE_REQ
Transmitter Precode Request.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When Set, this Port will request the transmitter to use Precoding by setting the Precoding Request bit in the TS1s/TS2s it transmits prior to entry to Recovery.Speed. |
|
[08:08] RO/V |
TX_PRECODING_ON
Transmitter Precoding On. This field indicates whether the Receiver asked this transmitter to enable Precoding. This bit is cleared on DL_Down.
Reset: hex:0x0;
|
[07:06] RO/V |
RX_ENH_LINK_BEHAVIOR_CTRL
Received Enhanced Link Behavior Control. This field contains the Enhanced Link Behavior Control bits from the most recent TS1 or TS2 received in the Polling or Configuration states.
Reset: hex:0x0;
|
[05:05] RO/V |
MOD_TS_RCVD
Modified TS Received. This bit is Cleared when the Link is Down. This bit is Set when the Modified TS1/TS2 Ordered Set is received.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
If Set, Received Modified TS Data 1 Register and Received Modified TS Data 2 Register contain meaningful data. |
|
[04:04] RW/1C/V |
LINK_EQ_32G_REQ
Link Equalization Request 32.0GT/s. This bit is Set by hardware to request the 32.0 GT/s Link equalization process to be performed on the Link. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
|
[03:03] RO/V |
EQ_32G_CPL_P3
Equalization 32.0GT/s Phase 3 Successful. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When set to 1b, this bit indicates that Phase 3 of the 32.0 GT/s Transmitter Equalization procedure has successfully completed. |
|
[02:02] RO/V |
EQ_32G_CPL_P2
Equalization 32.0GT/s Phase 2 Successful. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When set to 1b, this bit indicates that Phase 2 of the 32.0 GT/s Transmitter Equalization procedure has successfully completed. |
|
[01:01] RO/V |
EQ_32G_CPL_P1
Equalization 32.0GT/s Phase 1 Successful. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When set to 1b, this bit indicates that Phase 1 of the 32.0 GT/s Transmitter Equalization procedure has successfully completed. |
|
[00:00] RO/V |
EQ_32G_CPL
Equalization 32.0GT/s Complete. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When Set, this bit indicates that the 32.0 GT/s Transmitter Equalization procedure has completed. |
|
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+0x0000019c Register(32 bit) PL32G_RCVD_MOD_TS_DATA1_REG
Received Modified TS Data 1 Register.
This register contains the values received in the Modified TS1/TS2 Ordered Set.
If PCI Express (Usage Mode 0) is the only one supported by a Port, this register is permitted to be hardwired to 0000 0000h by the controller.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100019c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RCVD_MOD_TS_VENDER_ID |
RCVD_MOD_TS_INFO1 |
RCVD_MOD_TS_USAGE_MODE |
| Access |
RO/V |
RO/V |
RO/V |
[31:16] RO/V |
RCVD_MOD_TS_VENDER_ID
Received Modified TS Vendor ID. If Modified TS Received is Set, this field contains the Modified TS Vendor ID field from the Modified TS1/TS2 Ordered Set received. If Modified TS Received is Clear, this field contains 0000h. - 15:8 -- Contain the value of Symbol 11. - 7:0 -- Contain the value of Symbol 10. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0000h.
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| Ini_value |
0x0 |
Zero value. |
| Last_value |
0x0ffff |
Last value. |
|
[15:03] RO/V |
RCVD_MOD_TS_INFO1
Received Modified TS Information 1. If Modified TS Received is Set, this field contains the Modified TS Information 1 field from the Modified TS1/TS2 Ordered Set. If Modified TS Received is Clear, this field contains 0 0000 0000 0000b. - 15:8 -- contain the value of Symbol 9 - 7:3 -- contain bits 7:3 of Symbol 8 If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0 0000 0000 0000b by controller.
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| default |
0x0 |
Zero value. |
| maximum |
0x1fff |
Zero value. |
|
[02:00] RO/V |
RCVD_MOD_TS_USAGE_MODE
Received Modified TS Usage Mode. If Modified TS Received is Set, this field contains the Modified TS Usage field from the Modified TS1/TS2 Ordered Set. If Modified TS Received is Clear, this field contains 000b. Unused bits in this field are permitted to he hardwired by controller to 0b. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 000b.
Reset: hex:0x0;
|
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+0x000001a0 Register(32 bit) PL32G_RCVD_MOD_TS_DATA2_REG
Received Modified TS Data 2 Register.
This register contains the values received in Symbols 12 through 14 of the Modified TS1/TS2.
If Modified TS Usage Mode 1 Supported - Training Set Message and Modified TS Usage Mode 2 Supported - Alternate Protocol are both Clear, this register is permitted to be hardwired to 0000 0000h by the controller.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001a0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_26 |
RCVD_ALT_PROTOCOL_NEGO_STATUS |
RCVD_MOD_TS_INFO2 |
| Access |
RO |
RO |
RO/V |
[31:26] RO |
RSVDP_26
Reserved for future use.
Reset: hex:0x00;
|
[25:24] RO |
RCVD_ALT_PROTOCOL_NEGO_STATUS
Alternate Protocol Negotation Status. Indicates the status of the Alternate Protocol Negotiaiton. If Modified TS Usage Mode 1 Supported - Training Set Message and Modified TS Usage Mode 2 Supported - Alternate Protocol are both Clear, this register is permitted to be hardwired to 0000 0000h by controller. If Modified TS Usage Mode 2 Supported - Alternate Protocol is Clear, this bit is hardwired to 0b. If Modified TS Usage Mode Selected does not equal 2, this bit contains 0b.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disabled |
0x1 |
Alternate Protocol Negotiation disabled - Modified TS Usage Mode 2 Supported - Alternate Protocol is Set but Modified TS Usage Mode Selected was not 2 during the appropriate LTSSM State. |
| Failed |
0x2 |
Alternate Protocol Negotiation failed - Alternate Protocol Negotiation was attempted and did not locate a protocol that was supported on both ends of the Link. |
| Not_supported |
0x0 |
Alternate Protocol Negotiation not supported - Modified TS Usage Mode 2 Supported - Alternate Protocol is Clear. |
| Succeeded |
0x3 |
Alternate Protocol Negotiation succeeded - Alternate Protocol Negotiation located one or more protocols that were supported on both ends of the Link and the Downstream Port selected one of those protocols for use. |
|
[23:00] RO/V |
RCVD_MOD_TS_INFO2
Received Modified TS Information 2. If Modified TS Received is Set, this field contains the Modified TS Information 2 field from the received Modified TS1/TS2 Ordered Set. If Modified TS Received is Clear, this field contains 00 0000h. - 23:16 -- Contain the value of Symbol 12. - 16:8 -- Contain the value of Symbol 13. - 7:0 -- Contain the value of Symbol 14. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 00 0000h.
Reset: hex:0x000000;
| Valid Values |
| Name | Value(s) | Description |
| Maximum_val |
0x0ffffff |
Maximum value. |
| Minimum_val |
0x0 |
Zero value. |
|
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+0x000001a4 Register(32 bit) PL32G_TX_MOD_TS_DATA1_REG
Transmitted Modified TS Data 1 Register.
This register contains the values transmitted in the Modified TS1/TS2 Ordered Set.
If PCI Express (Usage Mode 0) is the only one supported by a Port, this register is permitted to be hardwired to 0000 0000h by the controller.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001a4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
TX_MOD_TS_VENDER_ID |
TX_MOD_TS_INFO1 |
TX_MOD_TS_USAGE_MODE |
| Access |
RO/V |
RO/V |
RO/V |
[31:16] RO/V |
TX_MOD_TS_VENDER_ID
Transmitted Modified TS Vendor ID. If Modified TS Received is Set, this field contains the Modified TS Vendor ID field from the last Modified TS1/TS2 Ordered Set transmitted during the most recent LTSSM State. - Bits 15:8 contain the value of Symbol 11. - Bits 7:0 contain the value of Symbol 10. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0000h by controller.
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| max_bit_val |
0x0ffff |
max bit value. |
| min_bit_value |
0x0 |
Zero value. |
|
[15:03] RO/V |
TX_MOD_TS_INFO1
Transmitted Modified TS Information 1. If Modified TS Received is Set, this field contains the Modified TS Information 1 field from Modified TS2 Ordered Set transmitted during the Configuration.Complete LTSSM State.
Bits [15:8] contain the value of Symbol 9
Bits [7:3] contain bits 7:3 of Symbol 8 If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 0 0000 0000 0000b.
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| init_0 |
0x0 |
Zero value. |
| value_13 |
0x1fff |
Zero value. |
|
[02:00] RO/V |
TX_MOD_TS_USAGE_MODE
Transmitted Modified TS Usage Mode. If Modified TS Received is Set, this field contains the Modified TS Usage field from the last Modified TS1/TS2 Ordered Set transmitted during the most recent LTSSM State. Unused bits in this field are permitted to he hardwired to 0b. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 000b.
Reset: hex:0x0;
|
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+0x000001a8 Register(32 bit) PL32G_TX_MOD_TS_DATA2_REG
Transmitted Modified TS Data 2 Register.
This register contains the values transmitted in Symbols 12 through 14 of the Modified TS1/TS2.
If Modified TS Usage Mode 1 Supported - Training Set Message and Modified TS Usage Mode 2 Supported - Alternate Protocol are both Clear, this register is permitted to be hardwired to 0000 0000h by the controller.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001a8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_26 |
TX_ALT_PROTOCOL_NEGO_STATUS |
TX_MOD_TS_INFO2 |
| Access |
RO |
RO |
RO/V |
[31:26] RO |
RSVDP_26
Reserved for future use.
Reset: hex:0x00;
|
[25:24] RO |
TX_ALT_PROTOCOL_NEGO_STATUS
Alternate Protocol Negotation Status. Indicates the status of the Alternate Protocol Negotiaiton. Encodings are : If Modified TS Usage Mode 1 Supported - Training Set Message and Modified TS Usage Mode 2 Supported - Alternate Protocol are both Clear, this register is permitted to be hardwired to 0000 0000h by controller. If Modified TS Usage Mode 2 Supported - Alternate Protocol is Clear, this bit is hardwired to 0b. If Modified TS Usage Mode Selected does not equal 2, this bit contains 0b.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disabled |
0x1 |
Alternate Protocol Negotiation disabled - Modified TS Usage Mode 2 Supported - Alternate Protocol is Set but Modified TS Usage Mode Selected was not 2 during the appropriate LTSSM State. |
| Failed |
0x2 |
Alternate Protocol Negotiation failed - Alternate Protocol Negotiation was attempted and did not locate a protocol that was supported on both ends of the Link. |
| Not_supported |
0x0 |
Alternate Protocol Negotiation not supported - Modified TS Usage Mode 2 Supported - Alternate Protocol is Clear. |
| Succeeded |
0x3 |
Alternate Protocol Negotiation succeeded - Alternate Protocol Negotiation located one or more protocols that were supported on both ends of the Link and the Downstream Port selected one of those protocols for use. |
|
[23:00] RO/V |
TX_MOD_TS_INFO2
Transmitted Modified TS Information 2. If Modified TS Received is Set, this field contains the Modified TS Information 2 field from the last Modified TS1/TS2 Ordered Set transmitted during the most recent LTSSM State.
Bits [23:16] contain the value of Symbol 12.
Bits [16:8] contain the value of Symbol 13.
Bits [7:0] contain the value of Symbol 14. If PCI Express (Usage Mode 0) is the only one supported, this field is permitted to be hardwired to 00 0000h by the controller.
Reset: hex:0x000000;
| Valid Values |
| Name | Value(s) | Description |
| initial_0 |
0x0 |
Zero value. |
| max_reset |
0x0ffffff |
Zero value. |
|
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+0x000001ac Register(32 bit) PL32G_CAP_OFF_20H_REG
32.0 GT/s Lane Equalization Control Register for Lane 0-3.
This register consists of control fields required for Lane 0-3 32.0 GT/s equalization.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001ac at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00004040 |
|
|
Unaffected |
0xffff0000 |
|
|
Undefined |
0xffff0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
USP_32G_TX_PRESET1 |
DSP_32G_TX_PRESET1 |
USP_32G_TX_PRESET0 |
DSP_32G_TX_PRESET0 |
| Access |
- |
RO |
RO |
RO |
RO |
[15:12] RO |
USP_32G_TX_PRESET1
Upstream Port 32.0 GT/s Transmitter Preset1. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field representss the value sent on Lane 1 during 32.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 1 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Case B also has a writable but not readable register internally with following access attributes. For case B and C, the writable register's value is set to implementation specific 32.0 GT/s Transmitter Preset bits in optional EQ TS2 OS if USP_SEND_8GT_EQ_TS2_DISABLE field of PORT_LOGIC - GEN3_RELATED_OFF register is 0b with RATE_SHADOW_SEL==10b.
Reset: hex:0x4;
|
[11:08] RO |
DSP_32G_TX_PRESET1
Downstream Port 32.0 GT/s Transmitter Preset1. Transmitter Preset of Lane 1 used for 32.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP, otherwise, this field is HwInit.
Reset: hex:0x0;
|
[07:04] RO |
USP_32G_TX_PRESET0
Upstream Port 32.0 GT/s Transmitter Preset0. - Case A: When Operating port is Downstream port and whether the Crosslink is supported or not, this field representss the value sent on Lane 0 during 32.0 GT/s equalization. - Case B: When Operating port is Upstream port and Crosslink Supported bit is 0, this field is intended for debug and diagnostics. It contains the value captured from Lane 0 during Link Equalization. - Case C: When Operating port is Upstream port and Crosslink Supported bit is 1, Field is not used or affected by the current Link Equalization. Field value will be used if a future crosslink negotiation switches the Operating Port Direction so that case A applies. For case A and C, Field is HwInit. For case B, Field is RO.
Case B also has a writable but not readable register internally with following access attributes. For case B and C, the writable register's value is set to implementation specific 32.0 GT/s Transmitter Preset bits in optional EQ TS2 OS if USP_SEND_8GT_EQ_TS2_DISABLE field of PORT_LOGIC - GEN3_RELATED_OFF register is 0b with RATE_SHADOW_SEL==10b.
Reset: hex:0x4;
|
[03:00] RO |
DSP_32G_TX_PRESET0
Downstream Port 32.0 GT/s Transmitter Preset0. Transmitter Preset of Lane 0 used for 32.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. This field is ignored when the Port is operating as an Upstream Port. For an Upstream Port if Crosslink Supported is 0b, this field is RsvdP, otherwise, this field is HwInit.
Reset: hex:0x0;
|
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+0x000001b0 Register(32 bit) RAS_DES_CAP_HEADER_REG
Vendor-Specific Extended Capability Header.
The Vendor-Specific Extended Capability (VSEC Capability) is an optional Extended Capability that is permitted to be implemented by any PCI Express Function or RCRB.
This Register contains Capability Id, Capability Version and Next Offset value for Vendor-Specific Extended Capability.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001b0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x2b01000b |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
| Name |
NEXT_OFFSET |
CAP_VERSION |
EXTENDED_CAP_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x2b0;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x0fff |
Max value |
|
[19:16] RO |
CAP_VERSION
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. Value of this field is depends on the version of the specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x0f |
Max value |
|
[15:00] RO |
EXTENDED_CAP_ID
PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for the Vendor-Specific Extended Capability is 000Bh.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x000b;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffff |
Max value |
| MIN_VAL |
0x0 |
Min value |
|
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+0x000001b4 Register(32 bit) VENDOR_SPECIFIC_HEADER_REG
Vendor-Specific Header.
This Register field provides VSEC Length, VSEC ID and VSEC Rev(Version Number).
Vendor-specific software must qualify the associated Vendor ID of the PCI Express Function or RCRB before attempting to interpret the values in the VSEC ID or VSEC Rev fields.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001b4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x10040002 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
| Name |
VSEC_LENGTH |
VSEC_REV |
VSEC_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
VSEC_LENGTH
VSEC Length. This field indicates the number of bytes in the entire VSEC structure, including the Vendor-Specific Extended Capability Header, the Vendor-Specific Header, and the vendor-specific registers.
Reset: hex:0x100;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x0fff |
Max value |
|
[19:16] RO |
VSEC_REV
VSEC Rev. This field is a vendor-defined version number that indicates the version of the VSEC structure. Software must qualify the Vendor ID and VSEC ID before interpreting this field.
Reset: hex:0x4;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x0f |
Max value |
|
[15:00] RO |
VSEC_ID
VSEC ID. This field is a vendor-defined ID number that indicates the nature and format of the VSEC structure. Software must qualify the Vendor ID before interpreting this field.
Reset: hex:0x0002;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffff |
Max value |
| MIN_VAL |
0x0 |
Min value |
|
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+0x000001b8 Register(32 bit) EVENT_COUNTER_CONTROL_REG
Event Counter Control.
This is a viewport control register.
- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register.
- Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.
- Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.
- Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001b8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_28 |
EVENT_COUNTER_EVENT_SELECT |
RSVDP_12 |
EVENT_COUNTER_LANE_SELECT |
EVENT_COUNTER_STATUS |
RSVDP_5 |
EVENT_COUNTER_ENABLE |
EVENT_COUNTER_CLEAR |
| Access |
RO |
RW |
RO |
RW |
RO/V |
RO |
WS/V |
WS/V |
[31:28] RO |
RSVDP_28
Reserved for future use.
Reset: hex:0x0;
|
[27:16] RW |
EVENT_COUNTER_EVENT_SELECT
Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group - .. For detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x000;
| Valid Values |
| Name | Value(s) | Description |
| EBUF_OVERFLOW |
0x0 |
Ebuf Overflow |
| EBUF_UNDERRUN |
0x1 |
Ebuf Underrun |
| RX_MSG_TLP |
0x713 |
Rx Message TLP |
| TX_MEM_WRITE |
0x700 |
Tx Memory Write |
|
[15:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x0;
|
[11:08] RW |
EVENT_COUNTER_LANE_SELECT
Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0f |
Lane15 |
| MIN_VAL |
0x0 |
Lane0 |
|
[07:07] RO/V |
EVENT_COUNTER_STATUS
Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
Clear |
| SET |
0x1 |
Set |
|
[06:05] RO |
RSVDP_5
Reserved for future use.
Reset: hex:0x0;
|
[04:02] WS/V |
EVENT_COUNTER_ENABLE
Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default, all event counters are disabled. You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes. You can enable/disable all event counters by writing the 'all on' or 'all off' codes. The read value is always '0'. For other values no change.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ALL_OFF |
0x5 |
all off |
| ALL_ON |
0x7 |
all on |
| PER_EVENT_OFF |
0x1 |
per event off |
| PER_EVENT_ON |
0x3 |
per event on |
|
[01:00] WS/V |
EVENT_COUNTER_CLEAR
Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code. The read value is always '0'. Other values are reserved.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ALL_CLEAR |
0x3 |
all clear |
| NO_CHANGE |
0x0 |
no change |
| NO_CHANGE_2 |
0x2 |
no change |
| PER_CLEAR |
0x1 |
per clear |
|
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+0x000001bc Register(32 bit) EVENT_COUNTER_DATA_REG
Event Counter Data.
This viewport register returns the data selected by the following fields:
- EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG
- EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001bc at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EVENT_COUNTER_DATA |
| Access |
RO/V |
[31:00] RO/V |
EVENT_COUNTER_DATA
Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x0ffffffff |
Max value |
|
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+0x000001e0 Register(32 bit) EINJ_ENABLE_REG
Error Injection Enable.
Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers:
- 0: CRC Error: EINJ0_CRC_REG
- 1: Sequence Number Error: EINJ1_SEQNUM_REG
- 2: DLLP Error: EINJ2_DLLP_REG
- 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG
- 4: FC Credit Update Error: EINJ4_FC_REG
- 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG
- 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG
After the errors have been inserted by controller, it will clear each bit here.
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001e0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_7 |
ERROR_INJECTION6_ENABLE |
ERROR_INJECTION5_ENABLE |
ERROR_INJECTION4_ENABLE |
ERROR_INJECTION3_ENABLE |
ERROR_INJECTION2_ENABLE |
ERROR_INJECTION1_ENABLE |
ERROR_INJECTION0_ENABLE |
| Access |
RO |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
[31:07] RO |
RSVDP_7
Reserved for future use.
Reset: hex:0x0000000;
|
[06:06] RW/V |
ERROR_INJECTION6_ENABLE
Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select.
You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.
You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0. For more information, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[05:05] RW/V |
ERROR_INJECTION5_ENABLE
Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more information, see the EINJ5_SP_TLP_REG register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[04:04] RW/V |
ERROR_INJECTION4_ENABLE
Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more information, see the EINJ4_FC_REG register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[03:03] RW/V |
ERROR_INJECTION3_ENABLE
Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more information, see the EINJ3_SYMBOL_REG register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[02:02] RW/V |
ERROR_INJECTION2_ENABLE
Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more information, see the EINJ2_DLLP_REG register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[01:01] RW/V |
ERROR_INJECTION1_ENABLE
Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more information, see the EINJ1_SEQNUM_REG register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[00:00] RW/V |
ERROR_INJECTION0_ENABLE
Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more information, see the EINJ0_CRC_REG register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
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+0x000001e4 Register(32 bit) EINJ0_CRC_REG
Error Injection Control 0 (CRC Error).
Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows:
- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts.
- 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs.
- 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs).
- ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side.
- FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state.
- Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur.
- Parity of SKPOS. Lane error will be detected at the receiver side when in Non-Flit mode for Gen3 data rate. Data Parity errors will be detected at the receiver when in Non-Flit mode for Gen4 or higher data rate. Data Parity errors will be detected at the receiver when in Flit mode for Gen3 or higher data rate.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001e4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x01370000 |
|
|
Undefined |
0x01370000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
- |
- |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_25 |
- |
RSVDP_22 |
- |
RSVDP_19 |
- |
RSVDP_12 |
EINJ0_CRC_TYPE |
EINJ0_COUNT |
| Access |
RO |
- |
RO |
- |
RO |
- |
RO |
RW |
RW/V |
[31:25] RO |
RSVDP_25
Reserved for future use.
Reset: hex:0x00;
|
[23:22] RO |
RSVDP_22
Reserved for future use.
Reset: hex:0x0;
|
[19:19] RO |
RSVDP_19
Reserved for future use.
Reset: hex:0x0;
|
[15:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x0;
|
[11:08] RW |
EINJ0_CRC_TYPE
Error injection type. Selects the type of CRC error to be inserted. All encodings other than the defined encodings are reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ECRC_ERR |
0x0b |
(RX Path) ECRC error injection |
| FCRC_ERR_TLP |
0x4 |
(TX Path) TLP's FCRC error injection (128b/130b or 1b/1b) |
| LCRC_ERR |
0x08 |
(RX Path) LCRC error injection |
| PARITY_SKPOS_ERR |
0x6 |
(TX Path) Parity error of SKPOS (128b/130b or 1b/1b) |
| PARITY_TSOS_ERR |
0x5 |
(TX Path) Parity error of TSOS (128b/130b or 1b/1b) |
| TLP_ECRC_ERR |
0x3 |
(TX Path) New TLP's ECRC error injection |
| TLP_LCRC_ERR |
0x0 |
(TX Path) New TLP's LCRC error injection |
| _16b_CRC_ERR_ACK_NAK_DLLP |
0x1 |
(TX Path) 16bCRC error injection of ACK/NAK DLLP |
| _16b_CRC_ERR_UPD_FC |
0x2 |
(TX Path) 16bCRC error injection of Update-FC DLLP |
|
[07:00] RW/V |
EINJ0_COUNT
Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted.
If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b.
If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
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+0x000001e8 Register(32 bit) EINJ1_SEQNUM_REG
Error Injection Control 1 (Sequence Number Error).
Controls the sequence number of the specific TLPs and ACK/NAK DLLPs.
Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true:
- ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048
- (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048
TLP is treated as Duplicate TLP at the Rx side when all these conditions are true:
- Sequence Number != NEXT_RCV_SEQ
- (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048
TLP is treated as Bad TLP at the Rx side when all these conditions are true:
- Sequence Number != NEXT_RCV_SEQ and
- (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001e8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_29 |
EINJ1_BAD_SEQNUM |
RSVDP_9 |
EINJ1_SEQNUM_TYPE |
EINJ1_COUNT |
| Access |
RO |
RW |
RO |
RW |
RW/V |
[31:29] RO |
RSVDP_29
Reserved for future use.
Reset: hex:0x0;
|
[28:16] RW |
EINJ1_BAD_SEQNUM
Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP from the controller's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link. Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0fff |
+4095 |
| MIN_VAL |
0x1001 |
-4095 |
|
[15:09] RO |
RSVDP_9
Reserved for future use.
Reset: hex:0x00;
|
[08:08] RW |
EINJ1_SEQNUM_TYPE
Sequence number type. Selects the type of sequence number.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ACK_NAK_DLLP_ERR |
0x1 |
Insertion of ACK/NAK DLLP's SEQ# Error |
| TLP_ERR |
0x0 |
Insertion of New TLP's SEQ# error |
|
[07:00] RW/V |
EINJ1_COUNT
Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.
If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'.
If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
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+0x000001ec Register(32 bit) EINJ2_DLLP_REG
Error Injection Control 2 (DLLP Error).
Controls the transmission of DLLPs and inserts the following errors:
- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur.
- If "FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs).
- If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001ec at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_10 |
EINJ2_DLLP_TYPE |
EINJ2_COUNT |
| Access |
RO |
RW |
RW/V |
[31:10] RO |
RSVDP_10
Reserved for future use.
Reset: hex:0x000000;
|
[09:08] RW |
EINJ2_DLLP_TYPE
DLLP Type. Selects the type of DLLP errors to be inserted.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ACK_NACK_DLLP |
0x0 |
ACK/NAK DLLP's transmission block |
| NAK_DLLP |
0x2 |
Always Transmission for NAK DLLP. This value is not supported in Flit Mode. |
| UPD_FC_DLLP |
0x1 |
FC DLLP's transmission block |
| RSVD |
0x3 |
Reserved |
|
[07:00] RW/V |
EINJ2_COUNT
Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.
If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'.
If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'. This register is affected only when EINJ2_DLLP_TYPE =2'10b.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
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+0x000001f0 Register(32 bit) EINJ3_SYMBOL_REG
Error Injection Control 3 (Symbol Error).
When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols.
- If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM.
- If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.
When 128b/130b encoding is used, this register controls error insertion into the sync-header.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001f0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_11 |
EINJ3_SYMBOL_TYPE |
EINJ3_COUNT |
| Access |
RO |
RW |
RW/V |
[31:11] RO |
RSVDP_11
Reserved for future use.
Reset: hex:0x000000;
|
[10:08] RW |
EINJ3_SYMBOL_TYPE
Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. All encodings other than the defined encodings are reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COM_FTS |
0x3 |
COM/FTS(FTS Order set) |
| COM_IDL |
0x4 |
COM/IDL(E-Idle Order set) |
| COM_PAD_TS1 |
0x1 |
COM/PAD(TS1 Order set) |
| COM_PAD_TS2 |
0x2 |
COM/PAD(TS2 Order set) |
| COM_SKP |
0x7 |
COM/SKP(SKP Order set) |
| END_EDB |
0x5 |
END/EDB Symbol |
| RSVD_OR_INVRT_SYNC_HDR |
0x0 |
Invert sync header for 128b/130b or 1b/1b encoding or this field is reserved for 8b/10b encoding. |
| STP_SDP |
0x6 |
STP/SDP Symbol |
|
[07:00] RW/V |
EINJ3_COUNT
Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.
If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'.
If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
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+0x000001f4 Register(32 bit) EINJ4_FC_REG
Error Injection Control 4 (FC Credit Error).
Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types:
- Posted TLP Header credit
- Non-Posted TLP Header credit
- Completion TLP Header credit
- Posted TLP Data credit
- Non-Posted TLP Data credit
- Completion TLP Data credit
These errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001f4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_29 |
EINJ4_BAD_UPDFC_VALUE |
RSVDP_15 |
EINJ4_VC_NUMBER |
RSVDP_11 |
EINJ4_UPDFC_TYPE |
EINJ4_COUNT |
| Access |
RO |
RW |
RO |
RW |
RO |
RW |
RW/V |
[31:29] RO |
RSVDP_29
Reserved for future use.
Reset: hex:0x0;
|
[28:16] RW |
EINJ4_BAD_UPDFC_VALUE
Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0fff |
+4095 |
| MIN_VAL |
0x1001 |
-4095 |
|
[15:15] RO |
RSVDP_15
Reserved for future use.
Reset: hex:0x0;
|
[14:12] RW |
EINJ4_VC_NUMBER
VC Number. Indicates target VC Number.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x7 |
Min Value |
| MIN_VAL |
0x0 |
Min Value |
|
[11:11] RO |
RSVDP_11
Reserved for future use.
Reset: hex:0x0;
|
[10:08] RW |
EINJ4_UPDFC_TYPE
Update-FC type. Selects the credit type.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CMPL_TLP_DATA |
0x6 |
Completion TLP Data Credit value control |
| CMPL_TLP_HDR |
0x2 |
Completion TLP Header Credit value control |
| NON_POSTED_TLP_DATA |
0x5 |
Non-Posted TLP Data Credit value control |
| NON_POSTED_TLP_HDR |
0x1 |
Non-Posted TLP Header Credit value control |
| POSTED_TLP_DATA |
0x4 |
Posted TLP Data Credit value control |
| POSTED_TLP_HDR |
0x0 |
Posted TLP Header Credit value control |
| RSERVED |
0x3 |
Reserved |
| RSVD |
0x7 |
Reserved |
|
[07:00] RW/V |
EINJ4_COUNT
Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.
If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'.
If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
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+0x000001f8 Register(32 bit) EINJ5_SP_TLP_REG
Error Injection Control 5 (Specific TLP Error).
Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol.
- For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side.
- For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but does not ensure that the errors are continuously inserted into TLPs.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001f8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_9 |
EINJ5_SPECIFIED_TLP |
EINJ5_COUNT |
| Access |
RO |
RW |
RW/V |
[31:09] RO |
RSVDP_9
Reserved for future use.
Reset: hex:0x000000;
|
[08:08] RW |
EINJ5_SPECIFIED_TLP
Specified TLP. Selects the specified TLP to be inserted.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DUPLICATE_DLLP |
0x0 |
Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. |
| NULLIFIED_TLP |
0x1 |
Generates Nullified TLP (Original TLP will be stored in retry buffer). |
|
[07:00] RW/V |
EINJ5_COUNT
Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.
If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'.
If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
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+0x000001fc Register(32 bit) EINJ6_COMPARE_POINT_H0_REG
Error Injection Control 6 (Compare Point Header DWORD #0).
Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010001fc at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_POINT_H0 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_POINT_H0
Packet Compare Point: 1st DWORD.
Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
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+0x00000200 Register(32 bit) EINJ6_COMPARE_POINT_H1_REG
Error Injection Control 6 (Compare Point Header DWORD #1).
Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000200 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_POINT_H1 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_POINT_H1
Packet Compare Point: 2nd DWORD.
Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
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+0x00000204 Register(32 bit) EINJ6_COMPARE_POINT_H2_REG
Error Injection Control 6 (Compare Point Header DWORD #2).
Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000204 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_POINT_H2 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_POINT_H2
Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
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+0x00000208 Register(32 bit) EINJ6_COMPARE_POINT_H3_REG
Error Injection Control 6 (Compare Point Header DWORD #3).
Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000208 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_POINT_H3 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_POINT_H3
Packet Compare Point: 4th DWORD.
Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
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+0x0000020c Register(32 bit) EINJ6_COMPARE_VALUE_H0_REG
Error Injection Control 6 (Compare Value Header DWORD #0).
Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100020c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_VALUE_H0 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_VALUE_H0
Packet Compare Value: 1st DWORD.
Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
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+0x00000210 Register(32 bit) EINJ6_COMPARE_VALUE_H1_REG
Error Injection Control 6 (Compare Value Header DWORD #1).
Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000210 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_VALUE_H1 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_VALUE_H1
Packet Compare Value: 2nd DWORD.
Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000214 Register(32 bit) EINJ6_COMPARE_VALUE_H2_REG
Error Injection Control 6 (Compare Value Header DWORD #2).
Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000214 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_VALUE_H2 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_VALUE_H2
Packet Compare Value: 3rd DWORD.
Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000218 Register(32 bit) EINJ6_COMPARE_VALUE_H3_REG
Error Injection Control 6 (Compare Value Header DWORD #3).
Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the EINJ6_TLP_REG register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000218 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_COMPARE_VALUE_H3 |
| Access |
RW |
[31:00] RW |
EINJ6_COMPARE_VALUE_H3
Packet Compare Value: 4th DWORD.
Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x0000021c Register(32 bit) EINJ6_CHANGE_POINT_H0_REG
Error Injection Control 6 (Change Point Header DWORD #0).
Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100021c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_POINT_H0 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_POINT_H0
Packet Change Point: 1st DWORD.
Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000220 Register(32 bit) EINJ6_CHANGE_POINT_H1_REG
Error Injection Control 6 (Change Point Header DWORD #1).
Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000220 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_POINT_H1 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_POINT_H1
Packet Change Point: 2nd DWORD.
Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000224 Register(32 bit) EINJ6_CHANGE_POINT_H2_REG
Error Injection Control 6 (Change Point Header DWORD #2).
Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000224 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_POINT_H2 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_POINT_H2
Packet Change Point: 3rd DWORD.
Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000228 Register(32 bit) EINJ6_CHANGE_POINT_H3_REG
Error Injection Control 6 (Change Point Header DWORD #3).
Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000228 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_POINT_H3 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_POINT_H3
Packet Change Point: 4th DWORD.
Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x0000022c Register(32 bit) EINJ6_CHANGE_VALUE_H0_REG
Error Injection Control 6 (Change Value Header DWORD #0).
Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100022c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_VALUE_H0 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_VALUE_H0
Packet Change Value: 1st DWORD.
Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).
Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000230 Register(32 bit) EINJ6_CHANGE_VALUE_H1_REG
Error Injection Control 6 (Change Value Header DWORD #1).
Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000230 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_VALUE_H1 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_VALUE_H1
Packet Change Value: 2nd DWORD.
Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).
Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000234 Register(32 bit) EINJ6_CHANGE_VALUE_H2_REG
Error Injection Control 6 (Change Value Header DWORD #2).
Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000234 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_VALUE_H2 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_VALUE_H2
Packet Change Value: 3rd DWORD.
Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).
Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x00000238 Register(32 bit) EINJ6_CHANGE_VALUE_H3_REG
Error Injection Control 6 (Change Value Header DWORD #3).
Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.
Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the EINJ6_TLP_REG register.
Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000238 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EINJ6_CHANGE_VALUE_H3 |
| Access |
RW |
[31:00] RW |
EINJ6_CHANGE_VALUE_H3
Packet Change Value: 4th DWORD.
Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).
Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x0000023c Register(32 bit) EINJ6_TLP_REG
Error Injection Control 6 (Packet Error).
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.
The type and number of errors are specified by the this register.
The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).
The type and number of errors are specified by the this register.
Only applies when EINJ6_INVERTED_CONTROL in this register =0.
The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true.
- Using 128b/130b encoding
- Injecting errors into TLP Length field / TLP digest bit
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100023c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_12 |
EINJ6_PACKET_TYPE |
EINJ6_INVERTED_CONTROL |
EINJ6_COUNT |
| Access |
RO |
RW |
RW |
RW/V |
[31:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x00000;
|
[11:09] RW |
EINJ6_PACKET_TYPE
Packet type. Selects the TLP packets to inject errors into. All encodings other than the specified encodings are reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| HEADER |
0x0 |
TLP Header |
| TLP_FIRST_4_DW |
0x1 |
TLP Prefix 1st 4-DWORDs |
| TLP_SECOND_DW |
0x2 |
TLP Prefix 2nd -DWORDs |
|
[08:08] RW |
EINJ6_INVERTED_CONTROL
Inverted Error Injection Control. Encodded values given as above.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| IGNORE |
0x1 |
EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. |
| REPLACE |
0x0 |
EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. |
|
[07:00] RW/V |
EINJ6_COUNT
Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted.
If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'.
If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
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+0x00000250 Register(32 bit) SD_CONTROL1_REG
Silicon Debug Control 1.
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000250 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_24 |
LOW_POWER_INTERVAL |
TX_EIOS_NUM |
RSVDP_17 |
FORCE_DETECT_LANE_EN |
FORCE_DETECT_LANE |
| Access |
RO |
RW |
RW |
RO |
RW |
RW |
[31:24] RO |
RSVDP_24
Reserved for future use.
Reset: hex:0x00;
|
[23:22] RW |
LOW_POWER_INTERVAL
Low Power Entry Interval Time.
Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _160NS |
0x1 |
160ns |
| _320NS |
0x2 |
320ns |
| _40NS |
0x0 |
40ns |
| _640NS |
0x3 |
640ns |
|
[21:20] RW |
TX_EIOS_NUM
Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| G2_16_EIOS_OTHER_SPEED_8_EIOS |
0x2 |
(2.5GT/s, 8.0GT/s or higher) 8 or (5.0GT/s ) 16 |
| G2_2_EIOS_OTHER_SPEED_1_EIOS |
0x0 |
(2.5GT/s, 8.0GT/s or higher) 1 or (5.0GT/s ) 2 |
| G2_32_EIOS_OTHER_SPEED_16_EIOS |
0x3 |
(2.5GT/s, 8.0GT/s or higher) 16 or (5.0GT/s ) 32 |
| G2_8_EIOS_OTHER_SPEED_4_EIOS |
0x1 |
(2.5GT/s, 8.0GT/s or higher) 4 or (5.0GT/s ) 8 |
|
[19:17] RO |
RSVDP_17
Reserved for future use.
Reset: hex:0x0;
|
[16:16] RW |
FORCE_DETECT_LANE_EN
Force Detect Lane Enable.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. |
| CLEAR |
0x0 |
Clear |
|
[15:00] RW |
FORCE_DETECT_LANE
Force Detect Lane. This field is a bit vector of lanes to force receiver detection on. When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0000;
|
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+0x00000254 Register(32 bit) SD_CONTROL2_REG
Silicon Debug Control 2.
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000254 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_17 |
FRAMING_ERR_RECOVERY_DISABLE |
RSVDP_11 |
DIRECT_LPBKSLV_TO_EXIT |
DIRECT_POLCOMP_TO_DETECT |
DIRECT_RECIDLE_TO_CONFIG |
RSVDP_3 |
NOACK_FORCE_LINKDOWN |
RECOVERY_REQUEST |
HOLD_LTSSM |
| Access |
RO |
RW |
RO |
RW |
RW |
RW |
RO |
RW |
WS/V |
RW |
[31:17] RO |
RSVDP_17
Reserved for future use.
Reset: hex:0x0000;
|
[16:16] RW |
FRAMING_ERR_RECOVERY_DISABLE
Framing Error Recovery Disable.
This bit disables a transition to Recovery state when a Framing Error is occurred.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[15:11] RO |
RSVDP_11
Reserved for future use.
Reset: hex:0x00;
|
[10:10] RW |
DIRECT_LPBKSLV_TO_EXIT
Direct Loopback Slave To Exit.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state. |
| CLEAR |
0x0 |
Clear |
|
[09:09] RW |
DIRECT_POLCOMP_TO_DETECT
Direct Polling.Compliance to Detect.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state. |
| CLEAR |
0x0 |
Clear |
|
[08:08] RW |
DIRECT_RECIDLE_TO_CONFIG
Direct Recovery.Idle to Configuration.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state. |
| CLEAR |
0x0 |
Clear |
|
[07:03] RO |
RSVDP_3
Reserved for future use.
Reset: hex:0x00;
|
[02:02] RW |
NOACK_FORCE_LINKDOWN
Force LinkDown.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State. |
| CLEAR |
0x0 |
Clear |
|
[01:01] WS/V |
RECOVERY_REQUEST
Recovery Request.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization. |
| CLEAR |
0x0 |
Clear |
|
[00:00] RW |
HOLD_LTSSM
Hold and Release LTSSM.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
As long as this field is '1', the controller stays in the current LTSSM. |
| CLEAR |
0x0 |
Clear |
|
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+0x00000260 Register(32 bit) SD_STATUS_L1LANE_REG
Silicon Debug Status(Layer1 Per-lane).
This viewport register returns the data selected by the following field:
- LANE_SELECT in SD_STATUS_L1LANE_REG
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000260 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00180000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DESKEW_POINTER |
RSVDP_21 |
PIPE_TXELECIDLE |
PIPE_RXELECIDLE |
PIPE_RXVALID |
PIPE_DETECT_LANE |
PIPE_RXPOLARITY |
RSVDP_4 |
LANE_SELECT |
| Access |
RO/V |
RO |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
RO |
RW |
[31:24] RO/V |
DESKEW_POINTER
Deskew Pointer.
Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[23:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x0;
|
[20:20] RO/V |
PIPE_TXELECIDLE
PIPE:TxElecIdle.
Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
|
[19:19] RO/V |
PIPE_RXELECIDLE
PIPE:RxElecIdle.
Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
|
[18:18] RO/V |
PIPE_RXVALID
PIPE:RxValid.
Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[17:17] RO/V |
PIPE_DETECT_LANE
PIPE:Detect Lane.
Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[16:16] RO/V |
PIPE_RXPOLARITY
PIPE:RxPolarity.
Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[15:04] RO |
RSVDP_4
Reserved for future use.
Reset: hex:0x000;
|
[03:00] RW |
LANE_SELECT
Lane Select.
Lane Select register for Silicon Debug Status Register of Layer1-PerLane.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0f |
Lane15 |
| MIN_VAL |
0x0 |
Lane0 |
|
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+0x00000264 Register(32 bit) SD_STATUS_L1LTSSM_REG
Silicon Debug Status(Layer1 LTSSM).
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000264 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000200 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LTSSM_VARIABLE |
LANE_REVERSAL |
RSVDP_11 |
PIPE_POWER_DOWN |
FRAMING_ERR |
FRAMING_ERR_PTR |
| Access |
RO/V |
RO/V |
RO |
RO/V |
RW/1C/V |
RO/V |
[31:16] RO/V |
LTSSM_VARIABLE
LTSSM Variable.
Indicates internal LTSSM variables defined in the PCI Express Base Specification. For other value idle_to_rlock_transitioned.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| CHANGED_SPEED_RCVRY |
0x1 |
changed_speed_recovery |
| DIR_SPEED_CHANGE |
0x0 |
directed_speed_change |
| EQ_DONE_16GT |
0x7 |
equalization_done_16GT_data_rate |
| EQ_DONE_8GT |
0x6 |
equalization_done_8GT_data_rate |
| SEL_DE_EMPHASIS |
0x4 |
select_deemphasis |
| START_EQ_W_PRESET |
0x5 |
start_equalization_w_preset |
| SUCCESSFUL_SPEED_NEGO |
0x2 |
successful_speed_negotiation |
| UPCFG_CAPABLE |
0x3 |
upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. |
|
[15:15] RO/V |
LANE_REVERSAL
Lane Reversal Operation.
Receiver detected lane reversal.
This field is only valid in the L0 LTSSM state.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[14:11] RO |
RSVDP_11
Reserved for future use.
Reset: hex:0x0;
|
[10:08] RO/V |
PIPE_POWER_DOWN
PIPE:PowerDown.
Indicates PIPE PowerDown signal.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x2;
|
[07:07] RW/1C/V |
FRAMING_ERR
Framing Error.
Indicates Framing Error detection status.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[06:00] RO/V |
FRAMING_ERR_PTR
First Framing Error Pointer.
Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. - Received Unexpected Framing Token (Values 01h to 06h) - Received Unexpected STP Token (Values 11h to 13h) - Received Unexpected Block (Values 21h to 30h) All encodings other than the defined encodings are reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| AFTER_DATA_BLK_OS_BLK_NOT_SKP_EI_EIE |
0x22 |
When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state |
| AT_LEAST_1_SYM_IS_NOT_EIOS_FROM_4_SYM |
0x2c |
When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) |
| CONSECUTIVE_OS_WITHIN_DATA_IN_SKPOS_STATE |
0x29 |
When Receiving consecutive OS Blocks within a Data Stream in SKPOS state |
| CRC_STP_NOT_MATCH |
0x11 |
When Framing CRC in STP token did not match |
| CURRENT_NO_VALID_EDB_PREVIOUS_VALID_EDB |
0x2 |
When current token was not a valid EDB token and previous token was an EDB. (128/256 bit controller only) |
| DATA_STREAM_WITHOUT_3_CYCLE_DATA_STREAM_S |
0x24 |
When Data Stream without data over three cycles in Datastream state |
| EDS_RECEIVED_NOT_EXPECTED |
0x5 |
When EDS token was expected but not received or whenever an EDS token was received but not expected. |
| FRE_ERR_DESKEW_PKT_IN_PROGRESS |
0x6 |
When a framing error was detected in the deskew block while a packet has been in progress in token_finder. |
| NOT_16_EIEOS_SYM_RECEIVED |
0x2e |
When Not full 16 eieos symbols are received in EIEOS state |
| NOT_ALL_LANE_START_RECEVING_EIEOS_SAME_T |
0x2d |
When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state |
| NOT_ALL_LANE_START_RECEVING_EIOS_SAME_T |
0x2b |
When Not all active lanes receiving EIOS starting at same cycle time in EIOS state |
| NOT_ALL_LANE_START_RECEVING_SKP_OS_SAME_T |
0x27 |
When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state. Note that Standard SKP Ordered Set and Control SKP Ordered Set are treated as the same SKP Ordered Set for this check |
| NOT_RECEIVING_SKPOS_AFTER_SDS |
0x2f |
When Not Receiving an SKP OS following SDS in Data Stream in flit mode |
| OS_BLK_DURING_DATA_STREAM |
0x25 |
When OS Block during Data Stream in Datastream state |
| PARITY_STP_NOT_MATCH |
0x12 |
When Framing Parity in STP token did not match. |
| PHYSTATUS_ERR_IN_SKPOS_STATE |
0x2a |
When PHY status error was detected in SKPOS state |
| RECEIVING_SKPOS_UNEQUAL_LENGTH |
0x30 |
When Receiving SKP OS of unequal lengths across all Lanes in flit mode |
| RECEVING_OS_AFTER_SDS_IN_DATA_STREAM |
0x21 |
When Receiving an OS Block following SDS in Datastream state |
| RXSTATUS_ERR_DATA_STREAM_STATE |
0x26 |
When RxStatus Error was detected in Datastream state |
| SDP_RECEIVED_NOT_EXPECTED |
0x3 |
When SDP token was received but not expected. (128 bit & (x8 | x16) controller only) |
| STP_OR_SDP_OR_IDL_RECEIVED_NO_TLP_OR_DLLP |
0x1 |
When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception |
| STP_RECEIVED_NOT_EXPECTED |
0x4 |
When STP token was received but not expected. (128 bit & (x8 | x16) controller only) |
| TLP_LENGTH_SMALLER_THEN_5DW |
0x13 |
When Framing TLP Length in STP token was smaller than 5 DWORDs. |
| UNDEFINE_BLK_TYPE |
0x23 |
When Block with an undefined Block Type in Datastream state |
| _2_BLK_TIMEOUT_SKP_OS_SKPOS_STATE |
0x28 |
When a 2-Block timeout occurs for SKP OS in SKPOS state |
|
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+0x00000268 Register(32 bit) SD_STATUS_PM_REG
Silicon Debug Status(PM).
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000268 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x0000e000 |
|
|
Undefined |
0x0000e000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_31 |
PM_USP_PROT_STATE |
PM_L0S_STATE |
LATCHED_NFTS |
- |
PME_RESEND_FLAG |
PM_USP_LINK_STATE |
PM_DSP_PROT_STATE |
PM_DSP_LINK_STATE |
| Access |
RO |
RO/V |
RO/V |
RO/V |
- |
RW/1C/V |
RO/V |
RO/V |
RO/V |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:27] RO/V |
PM_USP_PROT_STATE
Internal PM USP Prot FSM state.
Indicates internal PM Upstream Port Protocol FSM State of Power Management controller.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| USP_PROT_ACTIVE |
0x2 |
Upstream Protocol Active |
| USP_PROT_ENTER_L0S |
0x3 |
Upstream Protocol Enter L0S |
| USP_PROT_ENTER_L1 |
0x4 |
Upstream Protocol Enter L1S |
| USP_PROT_ENTER_L23 |
0x08 |
Upstream Protocol enter L23 |
| USP_PROT_L1_BLOCK_TLP |
0x5 |
Upstream Protocol L1 Block TLP |
| USP_PROT_L1_WAIT_LAST_TLP_ACK |
0x6 |
Upstream Protocol L1 Wait Last TLP Acknowledge |
| USP_PROT_L1_WAIT_PMDLLP_ACK |
0x7 |
Upstream Protocol L1 Wait PMDLLP Acknowledge |
| USP_PROT_L23_BLOCK_TLP |
0x09 |
Upstream Protocol L23 Block TLP |
| USP_PROT_L23_WAIT_LAST_TLP_ACK |
0x0a |
Upstream Protocol L23 WAIT LAST TLP Acknowledge |
| USP_PROT_L23_WAIT_PMDLLP_ACK |
0x0b |
Upstream Protocol L23 Wait PMDLLP Acknowledge |
| USP_PROT_RECOVERY |
0x1 |
Upstream Protocol Recovery |
| USP_PROT_RST |
0x0 |
Upstream Protocol Reset |
| USP_PROT_WAIT_CXS_IDLE |
0x0e |
Upstream Protocol Wait CXS IDLE |
| USP_PROT_WAIT_LAST_PMDLLP |
0x0d |
Upstream Protocol WAIT LAST PMDLLP |
| USP_PROT_WAIT_PMCSR_CPL_SENT |
0x0c |
Upstream Protocol WAIT PMCSR CPL SENT |
| RSVD_15 |
0x0f |
Reserved |
|
[26:24] RO/V |
PM_L0S_STATE
Internal PM L0S FSM state.
Indicates internal PM L0S FSM state of Power Management controller.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| L0S_BLOCK_TLP |
0x1 |
L0S_BLOCK_TLP |
| L0S_ENTER_L0S |
0x2 |
L0S_ENTER_L0S |
| L0S_EXIT |
0x4 |
L0S_EXIT |
| L0S_IDLE |
0x0 |
L0S_IDLE |
| L0S_L0S |
0x3 |
L0S_L0S |
| RSVD_5 |
0x5 |
Reserved |
| RSVD_6 |
0x6 |
Reserved |
| RSVD_7 |
0x7 |
Reserved |
|
[23:16] RO/V |
LATCHED_NFTS
Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[12:12] RW/1C/V |
PME_RESEND_FLAG
PME Re-send flag.
When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[11:08] RO/V |
PM_USP_LINK_STATE
Internal PM USP Link FSM state.
Indicates internal PM Upstream Port Link FSM state of Power Management controller.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| USP_LINK_ABORT |
0x2 |
USP_LINK_ABORT |
| USP_LINK_L0 |
0x3 |
USP_LINK_L0 |
| USP_LINK_L1 |
0x6 |
USP_LINK_L1 |
| USP_LINK_L1_EXIT |
0x7 |
USP_LINK_L1_EXIT |
| USP_LINK_L1_LINK_ENTR_L1 |
0x5 |
USP_LINK_L1_LINK_ENTR_L1 |
| USP_LINK_L23RDY |
0x0b |
USP_LINK_L23RDY |
| USP_LINK_L23RDY_WAIT4ALIVE |
0x0c |
USP_LINK_L23RDY_WAIT4ALIVE |
| USP_LINK_L23_ENTR_L23 |
0x0a |
USP_LINK_L23_ENTR_L23 |
| USP_LINK_PREP_4L1 |
0x4 |
USP_LINK_PREP_4L1 |
| USP_LINK_PREP_4L23 |
0x09 |
USP_LINK_PREP_4L23 |
| USP_LINK_RECOVERY |
0x1 |
USP_LINK_RECOVERY |
| USP_LINK_RST |
0x0 |
USP_LINK_RST |
| USP_LINK_WAIT_DSTATE_UPDATE |
0x08 |
USP_LINK_WAIT_DSTATE_UPDATE |
| RSVD_13 |
0x0d |
Reserved |
| RSVD_14 |
0x0e |
Reserved |
| RSVD_15 |
0x0f |
Reserved |
|
[07:04] RO/V |
PM_DSP_PROT_STATE
Internal PM DSP Prot FSM state.
Indicates internal PM Downstream Port Protocol FSM state of Power Management controller.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DSP_PROT_ACTIVE |
0x2 |
DSP_PROT_ACTIVE |
| DSP_PROT_BLOCK_TLP |
0x7 |
DSP_PROT_BLOCK_TLP |
| DSP_PROT_ENTER_L0S |
0x0c |
DSP_PROT_ENTER_L0S |
| DSP_PROT_ENTER_L1 |
0x0a |
DSP_PROT_ENTER_L1 |
| DSP_PROT_ENTER_L23 |
0x0b |
DSP_PROT_ENTER_L23 |
| DSP_PROT_NAK_BLOCK_TLP |
0x4 |
DSP_PROT_NAK_BLOCK_TLP |
| DSP_PROT_RECOVERY |
0x1 |
DSP_PROT_RECOVERY |
| DSP_PROT_RESPOND_NAK |
0x3 |
DSP_PROT_RESPOND_NAK |
| DSP_PROT_RST |
0x0 |
DSP_PROT_RST |
| DSP_PROT_WAIT_CXS_IDLE |
0x0d |
DSP_PROT_WAIT_CXS_IDLE |
| DSP_PROT_WAIT_LAST_PMDLLP |
0x09 |
DSP_PROT_WAIT_LAST_PMDLLP |
| DSP_PROT_WAIT_LAST_TLP_ACK |
0x08 |
DSP_PROT_WAIT_LAST_TLP_ACK |
| DSP_PROT_WAIT_NAK_TIMER |
0x6 |
DSP_PROT_WAIT_NAK_TIMER |
| DSP_PROT_WAIT_NAK_TLP_ACK |
0x5 |
DSP_PROT_WAIT_NAK_TLP_ACK |
| RSVD_14 |
0x0e |
Reserved |
| RSVD_15 |
0x0f |
Reserved |
|
[03:00] RO/V |
PM_DSP_LINK_STATE
Internal PM DSP Link FSM state.
Indicates internal PM Downstream Port Link FSM state of Power Management controller.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DSP_LINK_ABORT |
0x0a |
DSP_LINK_ABORT |
| DSP_LINK_ACK_WAIT4IDLE |
0x3 |
DSP_LINK_ACK_WAIT4IDLE |
| DSP_LINK_ENTR_L1 |
0x7 |
DSP_LINK_ENTR_L1 |
| DSP_LINK_ENTR_L23 |
0x4 |
DSP_LINK_ENTR_L23 |
| DSP_LINK_L0 |
0x2 |
DSP_LINK_L0 |
| DSP_LINK_L1 |
0x08 |
DSP_LINK_L1 |
| DSP_LINK_L1_EXIT |
0x09 |
DSP_LINK_L1_EXIT |
| DSP_LINK_L23RDY |
0x5 |
DSP_LINK_L23RDY |
| DSP_LINK_L23RDY_WAIT4ALIVE |
0x6 |
DSP_LINK_L23RDY_WAIT4ALIVE |
| DSP_LINK_RECOVERY |
0x1 |
DSP_LINK_RECOVERY |
| DSP_LINK_RST |
0x0 |
DSP_LINK_RST |
| RSVD_11 |
0x0b |
Reserved |
| RSVD_12 |
0x0c |
Reserved |
| RSVD_13 |
0x0d |
Reserved |
| RSVD_14 |
0x0e |
Reserved |
| RSVD_15 |
0x0f |
Reserved |
|
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+0x0000026c Register(32 bit) SD_STATUS_L2_REG
Silicon Debug Status(Layer2).
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100026c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00fff000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_28 |
FC_INIT2 |
FC_INIT1 |
DLCMSM |
RX_ACK_SEQ_NO |
TX_TLP_SEQ_NO |
| Access |
RO |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
[31:28] RO |
RSVDP_28
Reserved for future use.
Reset: hex:0x0;
|
[27:27] RO/V |
FC_INIT2
FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[26:26] RO/V |
FC_INIT1
FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[25:24] RO/V |
DLCMSM
DLCMSM. Indicates the current DLCMSM.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DL_ACTIVE |
0x3 |
DL_ACTIVE |
| DL_FC_INIT |
0x1 |
DL_FC_INIT |
| DL_INACTIVE |
0x0 |
DL_INACTIVE |
|
[23:12] RO/V |
RX_ACK_SEQ_NO
Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0xfff;
|
[11:00] RO/V |
TX_TLP_SEQ_NO
Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x000;
|
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+0x00000270 Register(32 bit) SD_STATUS_L3FC_REG
Silicon Debug Status(Layer3 FC).
The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields:
- CREDIT_SEL_VC
- CREDIT_SEL_CREDIT_TYPE
- CREDIT_SEL_TLP_TYPE
- CREDIT_SEL_HD
SD_STATUS_L3FC_REG returns the header credit [7:0] (CREDIT_SEL_HD =0) and the data credit [11:0] (CREDIT_SEL_HD =1) even when the Scaled FC is supported.
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000270 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CREDIT_DATA1 |
CREDIT_DATA0 |
RSVDP_7 |
CREDIT_SEL_HD |
CREDIT_SEL_TLP_TYPE |
CREDIT_SEL_CREDIT_TYPE |
CREDIT_SEL_VC |
| Access |
RO/V |
RO/V |
RO |
RW |
RW |
RW |
RW |
[31:20] RO/V |
CREDIT_DATA1
Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x000;
|
[19:08] RO/V |
CREDIT_DATA0
Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x000;
|
[07:07] RO |
RSVDP_7
Reserved for future use.
Reset: hex:0x0;
|
[06:06] RW |
CREDIT_SEL_HD
Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DATA_CREDIT |
0x1 |
Data Credit |
| HEADER_CREDIT |
0x0 |
Header Credit |
|
[05:04] RW |
CREDIT_SEL_TLP_TYPE
Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPLETION |
0x2 |
Completion |
| NON_POSTED |
0x1 |
Non-Posted |
| POSTED |
0x0 |
Posted |
|
[03:03] RW |
CREDIT_SEL_CREDIT_TYPE
Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| RX |
0x0 |
Rx |
| TX |
0x1 |
Tx |
|
[02:00] RW |
CREDIT_SEL_VC
Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x7 |
VC7 |
| MIN_VAL |
0x0 |
VC0 |
|
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+0x00000274 Register(32 bit) SD_STATUS_L3_REG
Silicon Debug Status(Layer3).
Silicon Debug Status(Layer3).
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000274 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_8 |
MFTLP_STATUS |
MFTLP_POINTER |
| Access |
RO |
RW/1C/V |
RO/V |
[31:08] RO |
RSVDP_8
Reserved for future use.
Reset: hex:0x000000;
|
[07:07] RW/1C/V |
MFTLP_STATUS
Malformed TLP Status. Indicates malformed TLP has occurred.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[06:00] RO/V |
MFTLP_POINTER
First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. All encodings other than the defined encodings are reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| APPLICATION |
0x7f |
Application |
| ATMC_OP_ALIGN |
0x1 |
AtomicOp address alignment |
| ATMC_OP_BYTE_EN |
0x3 |
AtomicOp byte enable |
| ATMC_OP_OPERAND |
0x2 |
AtomicOp operand |
| BYTE_ENABLE |
0x0a |
Byte enable |
| CMPL_RULES |
0x0f |
Completion rules |
| INVALID_TC |
0x7 |
Invalid TC |
| INVALID_TLP_TYPE |
0x0e |
Invalid TLP type |
| MAX_PAYLOAD_SIZE |
0x5 |
Max payload size |
| MEM_ADDR_4KB_BOUNDARY |
0x0b |
Memory Address 4KB boundary |
| TLP_LENGTH_MISMATCH |
0x4 |
TLP length miss match |
| TLP_PREFIX_RULES |
0x0c |
TLP prefix rules |
| TLP_WITHOUT_TC0 |
0x6 |
Message TLP without TC0 |
| TRANSLATION_RULES |
0x0d |
Translation request rules |
| UNXPCTD_CRS_STATUS_CMPL_TLP |
0x09 |
Unexpected CRS status in Completion TLP |
| UNXPCTD_ROUTE_BIT_MSG_TLP |
0x08 |
Unexpected route bit in Message TLP |
|
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+0x00000280 Register(32 bit) SD_EQ_CONTROL1_REG
Silicon Debug EQ Control 1.
This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers.
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000280 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
FOM_TARGET |
FOM_TARGET_ENABLE |
RSVDP_18 |
EVAL_INTERVAL_TIME |
RSVDP_10 |
EXT_EQ_TIMEOUT |
RSVDP_6 |
EQ_RATE_SEL |
EQ_LANE_SEL |
| Access |
RW |
RW |
RO |
RW |
RO |
RW |
RO |
RW |
RW |
[31:24] RW |
FOM_TARGET
FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).
This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[23:23] RW |
FOM_TARGET_ENABLE
FOM Target Enable. Enables the FOM_TARGET fields.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[22:18] RO |
RSVDP_18
Reserved for future use.
Reset: hex:0x00;
|
[17:16] RW |
EVAL_INTERVAL_TIME
Eval Interval Time. Indicates interval time of RxEqEval assertion. This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _1US |
0x1 |
1us |
| _2US |
0x2 |
2us |
| _4US |
0x3 |
4us |
| _500NS |
0x0 |
500ns |
|
[15:10] RO |
RSVDP_10
Reserved for future use.
Reset: hex:0x00;
|
[09:08] RW |
EXT_EQ_TIMEOUT
Extends EQ Phase2/3 Timeout. This field is used when the LTSSM is in Recovery.EQ2/3. When this field is set, the value of EQ2/3 timeout is extended.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_TIMEOUT |
0x3 |
[EQ Master(DSP in EQ Phase3/USP in EQ Phase2)] No timeout or [EQ Slave(DSP in EQ Phase2/USP in EQ Phase3)] No timeout |
| _240MS_OR_248MS_OR_480MS_OR_496MS |
0x2 |
[EQ Master(DSP in EQ Phase3/USP in EQ Phase2) for 8.0GT/s, 16.0GT/s, 32GT/s] 240ms (x10) or [EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) for 8.0GT/s, 16.0GT/s, 32GT/s] 248ms (32ms +9*24ms) or [EQ Master(DSP in EQ Phase3/USP in EQ Phase2) for 64.0GT/s] 480ms (x10) or [EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) for 64.0GT/s] 496ms (64ms +9*48ms) |
| _24MS_OR_32MS_OR_48MS_OR_64MS |
0x0 |
[EQ Master(DSP in EQ Phase3/USP in EQ Phase2) for 8.0GT/s, 16.0GT/s, 32GT/s] 24ms (default) or [EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) for 8.0GT/s, 16.0GT/s, 32GT/s] 32ms (default) or [EQ Master(DSP in EQ Phase3/USP in EQ Phase2) for 64.0GT/s] 48ms (default) or [EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) for 64.0GT/s] 64ms (default) |
| _48MS_OR_56MS_OR_96MS_OR_112MS |
0x1 |
[EQ Master(DSP in EQ Phase3/USP in EQ Phase2) for 8.0GT/s, 16.0GT/s, 32GT/s] 48ms (x2) or [EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) for 8.0GT/s, 16.0GT/s, 32GT/s] 56ms (32ms+24ms) or [EQ Master(DSP in EQ Phase3/USP in EQ Phase2) for 64.0GT/s] 96ms (x2) or [EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) for 64.0GT/s] 112ms (64ms+48ms) |
|
[07:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x0;
|
[05:04] RW |
EQ_RATE_SEL
EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _16GT |
0x1 |
16.0GT/s Speed (include ESM data rate) |
| _32GT |
0x2 |
32.0GT/s Speed |
| _64GT |
0x3 |
64.0GT/s Speed |
| _8GT |
0x0 |
8.0GT/s Speed (include ESM data rate) |
|
[03:00] RW |
EQ_LANE_SEL
EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0f |
Lane15 |
| MIN_VAL |
0x0 |
Lane0 |
|
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+0x00000284 Register(32 bit) SD_EQ_CONTROL2_REG
Silicon Debug EQ Control 2.
This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000284 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_31 |
FORCE_LOCAL_TX_PRESET_ENABLE |
FORCE_LOCAL_RX_HINT_ENABLE |
FORCE_LOCAL_TX_COEF_ENABLE |
FORCE_LOCAL_TX_PRESET |
FORCE_LOCAL_RX_HINT_OR_FORCE_LOCAL_TX_2ND_PRE_CURSOR |
FORCE_LOCAL_TX_POST_CURSOR |
FORCE_LOCAL_TX_CURSOR |
FORCE_LOCAL_TX_PRE_CURSOR |
| Access |
RO |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:30] RW/V |
FORCE_LOCAL_TX_PRESET_ENABLE
Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[29:29] RW/V |
FORCE_LOCAL_RX_HINT_ENABLE
Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT_OR_FORCE_LOCAL_TX_2ND_PRE_CURSOR field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[28:28] RW/V |
FORCE_LOCAL_TX_COEF_ENABLE
Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_RX_HINT_OR_FORCE_LOCAL_TX_2ND_PRE_CURSOR - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR FORCE_LOCAL_RX_HINT_OR_FORCE_LOCAL_TX_2ND_PRE_CURSOR field is enabled only when CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is 64.0GT/s Speed.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[27:24] RW/V |
FORCE_LOCAL_TX_PRESET
Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[23:18] RW/V |
FORCE_LOCAL_RX_HINT_OR_FORCE_LOCAL_TX_2ND_PRE_CURSOR
If select rate in the EQ_RATE_SEL field is 8.0GT/s Speed, Bit [20:18] corresponds to Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. If CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is 64.0GT/s Speed, Force Local Transmitter 2nd Pre-Cursor. Bit [23:21] is not used. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s or 64.0 GT/s Speed, this feature is not available.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[17:12] RW/V |
FORCE_LOCAL_TX_POST_CURSOR
Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. If CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is 64.0GT/s Speed, Bit [17] is not used.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[11:06] RW/V |
FORCE_LOCAL_TX_CURSOR
Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[05:00] RW/V |
FORCE_LOCAL_TX_PRE_CURSOR
Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. If CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is 64.0GT/s Speed, Bit [5:4] is not used.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
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+0x00000288 Register(32 bit) SD_EQ_CONTROL3_REG
Silicon Debug EQ Control 3.
This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000288 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_29 |
FORCE_REMOTE_TX_COEF_ENABLE |
RSVDP_24 |
FORCE_REMOTE_TX_2ND_PRE_CURSOR |
FORCE_REMOTE_TX_POST_CURSOR |
FORCE_REMOTE_TX_CURSOR |
FORCE_REMOTE_TX_PRE_CURSOR |
| Access |
RO |
RW/V |
RO |
RW/V |
RW/V |
RW/V |
RW/V |
[31:29] RO |
RSVDP_29
Reserved for future use.
Reset: hex:0x0;
|
[28:28] RW/V |
FORCE_REMOTE_TX_COEF_ENABLE
Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_2ND_PRE_CURSOR - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR FORCE_REMOTE_TX_2ND_PRE_CURSOR field is enabled only when CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is 64.0GT/s Speed. This function can only be used when GEN3_EQ_FB_MODE = 0000b(Direction Change)
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[27:24] RO |
RSVDP_24
Reserved for future use.
Reset: hex:0x0;
|
[23:18] RW/V |
FORCE_REMOTE_TX_2ND_PRE_CURSOR
Force Remote Transmitter 2nd Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local PHY in dirchange mode. Bit [23:21] is not used. If select rate in the EQ_RATE_SEL field is other than 64.0GT/s Speed, this feature is not available. This field is reserved when CX_GEN6_SPEED is not set.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[17:12] RW/V |
FORCE_REMOTE_TX_POST_CURSOR
Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local PHY in dirchange mode. If CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is 64.0GT/s Speed, Bit [17] is not used.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[11:06] RW/V |
FORCE_REMOTE_TX_CURSOR
Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local PHY in dirchange mode.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[05:00] RW/V |
FORCE_REMOTE_TX_PRE_CURSOR
Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local PHY in dirchange mode. If CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is 64.0GT/s Speed, Bit [5:4] is not used.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
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+0x00000290 Register(32 bit) SD_EQ_STATUS1_REG
Silicon Debug EQ Status 1.
This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.
The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2).
- EQ_RULEA_VIOLATION
- EQ_RULEB_VIOLATION
- EQ_RULEC_VIOLATION
- EQ_RULED_VIOLATION
- EQ_REJECT_EVENT
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000290 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EQ_REMOTE_2ND_PRE_CURSOR |
RSVDP_8 |
EQ_REJECT_EVENT |
EQ_RULEC_VIOLATION |
EQ_RULEB_VIOLATION |
EQ_RULEA_VIOLATION |
EQ_RULED_VIOLATION |
EQ_CONVERGENCE_INFO |
EQ_SEQUENCE |
| Access |
RO/V |
RO |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
[31:26] RO/V |
EQ_REMOTE_2ND_PRE_CURSOR
EQ Remote 2nd Pre-Cursor. Indicates Remote 2nd pre cursor coefficient value. This field is reserved when CX_GEN6_SPEED is not set.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[25:08] RO |
RSVDP_8
Reserved for future use.
Reset: hex:0x00000;
|
[07:07] RO/V |
EQ_REJECT_EVENT
EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[06:06] RO/V |
EQ_RULEC_VIOLATION
EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.
This bit is automatically cleared when the controller starts EQ Master phase again.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[05:05] RO/V |
EQ_RULEB_VIOLATION
EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.
This bit is automatically cleared when the controller starts EQ Master phase again.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[04:04] RO/V |
EQ_RULEA_VIOLATION
EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.
This bit is automatically cleared when the controller starts EQ Master phase again.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[03:03] RO/V |
EQ_RULED_VIOLATION
EQ Rule D Violation. Indicates that coefficients rule D violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule D correspond to the rules d) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification. If select rate in the EQ_RATE_SEL field is other than 64.0GT/s Speed, this feature is not available. This field is reserved when CX_GEN6_SPEED is not set.
This bit is automatically cleared when the controller starts EQ Master phase again.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[02:01] RO/V |
EQ_CONVERGENCE_INFO
EQ Convergence Info. Indicates equalization convergence information. This bit is automatically cleared when the controller starts EQ Master phase again.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| EQ_NOT_ATTEMPTED |
0x0 |
Equalization is not attempted |
| EQ_SUCCESSFUL |
0x1 |
Equalization finished successfully |
| EQ_UNSUCCESSFUL |
0x2 |
Equalization finished unsuccessfully |
| RSVD |
0x3 |
Reserved |
|
[00:00] RO/V |
EQ_SEQUENCE
EQ Sequence. Indicates that the controller is starting the equalization sequence.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
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+0x00000294 Register(32 bit) SD_EQ_STATUS2_REG
Silicon Debug EQ Status 2.
This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.
Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000294 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
EQ_LOCAL_FOM_VALUE |
EQ_LOCAL_RX_HINT_OR_EQ_LOCAL_2ND_PRE_CURSOR |
EQ_LOCAL_POST_CURSOR |
EQ_LOCAL_CURSOR |
EQ_LOCAL_PRE_CURSOR |
| Access |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
[31:24] RO/V |
EQ_LOCAL_FOM_VALUE
EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[23:18] RO/V |
EQ_LOCAL_RX_HINT_OR_EQ_LOCAL_2ND_PRE_CURSOR
If select rate in the EQ_RATE_SEL field is 8.0GT/s Speed, Bit [20:18] corresponds to EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is 64.0GT/s Speed, EQ Local 2nd Pre-Cursor. Indicates Local 2nd pre cursor coefficient value. If CX_GEN6_SPEED is set and select rate in the EQ_RATE_SEL field is other than 8.0GT/s or 64.0 GT/s Speed, this feature is not available.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[17:12] RO/V |
EQ_LOCAL_POST_CURSOR
EQ Local Post-Cursor. Indicates Local post cursor coefficient value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[11:06] RO/V |
EQ_LOCAL_CURSOR
EQ Local Cursor. Indicates Local cursor coefficient value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[05:00] RO/V |
EQ_LOCAL_PRE_CURSOR
EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
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+0x00000298 Register(32 bit) SD_EQ_STATUS3_REG
Silicon Debug EQ Status 3.
This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.
Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).
For more information, see the RAS DES section in the Controller Operations chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000298 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_30 |
EQ_REMOTE_FS |
EQ_REMOTE_LF |
EQ_REMOTE_POST_CURSOR |
EQ_REMOTE_CURSOR |
EQ_REMOTE_PRE_CURSOR |
| Access |
RO |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
[31:30] RO |
RSVDP_30
Reserved for future use.
Reset: hex:0x0;
|
[29:24] RO/V |
EQ_REMOTE_FS
EQ Remote FS. Indicates Remote FS value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[23:18] RO/V |
EQ_REMOTE_LF
EQ Remote LF. Indicates Remote LF value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[17:12] RO/V |
EQ_REMOTE_POST_CURSOR
EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[11:06] RO/V |
EQ_REMOTE_CURSOR
EQ Remote Cursor. Indicates Remote cursor coefficient value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
|
[05:00] RO/V |
EQ_REMOTE_PRE_CURSOR
EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
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+0x000002b0 Register(32 bit) DATA_LINK_FEATURE_EXT_HDR_OFF
Data Link Feature Extended Capability Header Register.
This register provides capability ID, capability version, and next offset value.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002b0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x2bc10025 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
| Name |
DLINK_NEXT_OFFSET |
DLINK_CAP_VERSION |
DLINK_EXT_CAP_ID |
| Access |
RO/V |
RO |
RO |
[31:20] RO/V |
DLINK_NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h, if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh. The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x2bc;
|
[19:16] RO |
DLINK_CAP_VERSION
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field depends on the version of the specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
|
[15:00] RO |
DLINK_EXT_CAP_ID
Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for Data Link Feature is 0025h.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0025;
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+0x000002b4 Register(32 bit) DATA_LINK_FEATURE_CAP_OFF
Data Link Feature Capabilities Register.
This register provides description about extended feature.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002b4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x80000001 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
| Name |
DL_FEATURE_EXCHANGE_EN |
RSVDP_23 |
FUTURE_FEATURE_SUPPORTED |
LCL_L0P_EXIT_LTNCY |
LCL_EXTENDED_VC_CNT |
LCL_IMMEDIATE_READINESS |
SCALED_FLOW_CNTL_SUPPORTED |
| Access |
RO |
RO |
RO |
RO/V |
RO |
RO |
RO |
[31:31] RO |
DL_FEATURE_EXCHANGE_EN
Data Link Feature Exchange Enable. If Set, this bit indicates that this Port will enter the DL_Feature negotiation state.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Reset: hex:0x1;
|
[30:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x00;
|
[22:08] RO |
FUTURE_FEATURE_SUPPORTED
Local Future Data Link Feature Supported.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0000;
|
[07:05] RO/V |
LCL_L0P_EXIT_LTNCY
This is a data link parameter.
This field indicates this Port's knowledge of L0p Exit Latency. The value reported is the larger of Port L0p Exit Latency and Retimer L0p Exit Latency. The actual time required to widen the Link is the larger of Local L0p Exit Latency and Remote L0p Exit Latency. The Downstream Port's Retimer L0p Exit Latency should include retimers that are part of the system. The Upstream Port's Retimer L0p Exit Latency should include retimers that are part of the add-in card. Defined encodings are: This field is meaningful in Flit Mode. In Non-Flit Mode, this field must be zero.
Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_FLIT_MODE_SUPP ? RO : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_FLIT_MODE_SUPP ? DBI_WRITABLE : RO
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| EIGHT_TO_SIXTEEN_MICRO |
0x4 |
8 μs to less than 16 μs. |
| FOUR_TO_EIGHT_MICRO |
0x3 |
4 μs to less than 8 μs. |
| LESS_THAN_MICRO |
0x0 |
Less than 1μs. |
| MORE_THAN_SIXTY_FOUR_MICRO |
0x7 |
More than 64 μs. |
| ONE_TO_TWO_MICRO |
0x1 |
1 μs to less than 2 μs. |
| SIXTEEN_TO_THIRTY_TWO_MICRO |
0x5 |
16 μs to less than 32 μs. |
| THIRTY_TWO_SIXTY_FOUR_MICRO |
0x6 |
32 μs-64 μs. |
| TWO_TO_FOUR_MICRO |
0x2 |
2 μs to less than 4 μs. |
|
[04:02] RO |
LCL_EXTENDED_VC_CNT
Local Extended VC Count.
This field indicates the number of VC resources supported by this port. This is tte value of the extended VC count field in either the multi-function virtual channel extended capability or the virtual channel extended capability (With capability ID 0002h).
This field is meaningful in Flit Mode. In Non-Flit Mode, this field must be zero.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Reset: hex:0x0;
|
[01:01] RO |
LCL_IMMEDIATE_READINESS
Local Immediate Readiness.
This Bit indicates that all non-virtual functions in this port hace immediate readiness set.
This bit MUST@FLIT be meaningful. in non-Flit mode, this bit is meaningful when set, but when clear indicates either some non-virtual function has immediate readiness clear or that this port is not providing this information.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Reset: hex:0x0;
|
[00:00] RO |
SCALED_FLOW_CNTL_SUPPORTED
Local Scaled Flow Control Supported.
This bit indicates that this Port supports Scaled Flow Control Feature
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Reset: hex:0x1;
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+0x000002b8 Register(32 bit) DATA_LINK_FEATURE_STATUS_OFF
Data Link Feature Status Register.
This register provides status of the capability of data link feature.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002b8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DATA_LINK_FEATURE_STATUS_VALID |
RSVDP_23 |
REMOTE_RESERVED |
REMOTE_L0P_EXIT_LTNCY |
REMOTE_EXTENDED_VC_CNT |
REMOTE_IMMEDIATE_READINESS |
REMOTE_SCALED_FLOW_CNTL_SUPPORTED |
| Access |
RO/V |
RO |
RO/V |
RO/V |
RO/V |
RO/V |
RO/V |
[31:31] RO/V |
DATA_LINK_FEATURE_STATUS_VALID
Remote Data Link Feature Supported Valid. This field indicates that the Port has received a Data Link Feature DLLP in state DL_Feature and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields are meaningful. This field is Cleared on entry to state DL_Inactive.
Reset: hex:0x0;
|
[30:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x00;
|
[22:08] RO/V |
REMOTE_RESERVED
Remote Data Link RSVDP [22:8].
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| Rsvd |
0x0 |
Bits are RSVDP |
|
[07:05] RO/V |
REMOTE_L0P_EXIT_LTNCY
Remote L0p Exit Latency. Data Link Parameter This field indicates the remote Port's L0p Exit Latency. The value reported indicates the length of time the remote Port requires to complete widening a link using L0p. If the remote Port does not support L0p, this field must contain 000b. Defined encodings are:
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Less_1u |
0x0 |
Less than 1 μs |
| More_64u |
0x7 |
More than 64 μs |
| _16u_Less_32u |
0x5 |
16 μs to less than 32 μs |
| _1u_Less_2u |
0x1 |
1 μs to less than 2 μs |
| _2u_Less_4u |
0x2 |
2 μs to less than 4 μs |
| _32u_64u |
0x6 |
32 μs-64 μs |
| _4u_Less_8u |
0x3 |
4 μs to less than 8 μs |
| _8u_Less_16u |
0x4 |
8 μs to less than 16 μs |
|
[04:02] RO/V |
REMOTE_EXTENDED_VC_CNT
Extended VC count.
This field indicates the number of the VC resources supported by the sending port. This is the value of the extended VC count field in either the Multi-Function Virtual Channel extended capability or the virtual channel extended capability (with capabality ID 0002h).
This field is meaningful in Flit Mode. In non-flit mode, This field must be zero.
Reset: hex:0x0;
|
[01:01] RO/V |
REMOTE_IMMEDIATE_READINESS
Remote Immediate Readiness.
This bit indicates that all non-virtual functions in the remote port have Immediate Readiness Set.
In Flit Mode, This bit is always meaningful. In Non-Flit Mode, This bit is meaningful when set, But when clear indicates either that some non-virtual function has Immediate Readiness clear or that the remote port is not providing this information.
Reset: hex:0x0;
|
[00:00] RO/V |
REMOTE_SCALED_FLOW_CNTL_SUPPORTED
Remote Scaled Flow Control Supported.
This bit indicates that the Remote Port supports the Scaled Flow Control Feature.
Reset: hex:0x0;
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+0x000002bc Register(32 bit) VSECDMA_EXT_CAP_HDR_OFF
PCIe Extended Capability ID, Capability Version, and Next Capability Offset Register.
This register provides capability ID, capability version, and next capability offset for PCIe extended capability structure.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002bc at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x2d41000b |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
| Name |
NEXT_OFFSET |
CAP |
ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
NEXT_OFFSET
Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh. The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x2d4;
|
[19:16] RO |
CAP
Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. A version of the specification that changes the Extended Capability in a way that is not otherwise identifiable (that is, through a new Capability field) is permitted to increment this field. All such changes to the Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as Functions reporting any such Capability Version numbers will contain a Capability structure that is compatible with that piece of software.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x1;
|
[15:00] RO |
ID
PCI Express Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x000b;
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+0x000002c0 Register(32 bit) VSECDMA_VENDOR_SPECIFIC_HDR_OFF
Vendor Specific Header Register.
This Register provides VSEC Length, VSEC ID, and VSEC Rev(Version Number).
Vendor-specific software must qualify the associated Vendor ID of the PCI Express Function or RCRB before attempting to interpret the values in the VSEC ID or VSEC Rev fields.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002c0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x01800006 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
| Name |
VSEC_LENGTH |
VSEC_REV |
VSEC_ID |
| Access |
RO |
RO |
RO |
[31:20] RO |
VSEC_LENGTH
VSEC Length. This field indicates the number of bytes in the entire VSEC structure, including the Vendor-Specific Extended Capability Header, the Vendor-Specific Header, and the vendor-specific registers.
Reset: hex:0x018;
|
[19:16] RO |
VSEC_REV
VSEC Rev. This field is a vendor-defined version number that indicates the version of the VSEC structure. Software must qualify the Vendor ID and VSEC ID before interpreting this field.
Reset: hex:0x0;
|
[15:00] RO |
VSEC_ID
VSEC ID. This field is a vendor-defined ID number that indicates the nature and format of the VSEC structure. Software must qualify the Vendor ID before interpreting this field.
Reset: hex:0x0006;
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+0x000002c4 Register(32 bit) VSECDMA_DEVICE_INFORMATION_OFF
DMA and related AXI Bridge Implementation Information.
This register provides DMA and AXI Bridge implementation-specific information:
- DMA Architecture: Legacy DMA or Hyper DMA (HDMA).
- Register Location: Port-logic or Mapped to a Function and BAR.
- Register Map: Legacy DMA or HDMA.
- Channel Separation: Address distance between read and write channels.
- AXI Bridge: Used or Not Used
- AXI Manager Bus Specification: AXI Manager Bus Width, Burst Length, and Boundary Pointer Width
You must use this information along with the IP version registers:
- PCIE_VERSION_NUMBER_OFF
- PCIE_VERSION_TYPE_OFF
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002c4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x35a80407 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
| Name |
RSVDP_30 |
MASTER_PAGE_BOUNDARY_POINTER_WIDTH |
MASTER_BURST_LENGTH |
MASTER_BUS_WIDTH |
AXI |
CHANNEL_SEPARATION |
PFN |
BARN |
RSVDP_3 |
MAP_FORMAT |
| Access |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
[31:30] RO |
RSVDP_30
Reserved for future use.
Reset: hex:0x0;
|
[29:26] RO |
MASTER_PAGE_BOUNDARY_POINTER_WIDTH
This field provides address page boundary information. It reports the value of CC_MSTR_PAGE_BOUNDARY_PW configuration parameter.
Reset: hex:0xd;
|
[25:23] RO |
MASTER_BURST_LENGTH
Reports the CC_MSTR_BURST_LEN configuration parameter.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| MSTR_BRSTLEN_0 |
0x0 |
Reserved |
| MSTR_BRSTLEN_128 |
0x6 |
128 beats |
| MSTR_BRSTLEN_16 |
0x3 |
16 beats |
| MSTR_BRSTLEN_256 |
0x7 |
256 beats |
| MSTR_BRSTLEN_32 |
0x4 |
32 beats |
| MSTR_BRSTLEN_4 |
0x1 |
4 beats |
| MSTR_BRSTLEN_64 |
0x5 |
64 beats |
| MSTR_BRSTLEN_8 |
0x2 |
8 beats |
|
[22:20] RO |
MASTER_BUS_WIDTH
This field provides information regarding the AXI manager data bus width. It reports the value of MASTER_BUS_DATA_WIDTH configuration parameter.
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| MSTR_BUSWD_128 |
0x2 |
128 bits |
| MSTR_BUSWD_256 |
0x3 |
256 bits |
| MSTR_BUSWD_32 |
0x0 |
32 bits |
| MSTR_BUSWD_512 |
0x4 |
512 bits |
| MSTR_BUSWD_64 |
0x1 |
64 bits |
|
[19:19] RO |
AXI
This field provides information about AXI interface usage. It reports the value of AXI_POPULATED configuration parameter.
Reset: hex:0x1;
|
[18:16] RO |
CHANNEL_SEPARATION
If the MAP_FORMAT is set to HDMA_NATIVE, this field specifies the read write channel address separation. Other values are reserved.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CHSEP_16K |
0x6 |
16k separated |
| CHSEP_1K |
0x2 |
1k separated |
| CHSEP_256 |
0x0 |
256 separated |
| CHSEP_2K |
0x3 |
2k separated |
| CHSEP_32K |
0x7 |
32k separated |
| CHSEP_4K |
0x4 |
4k separated |
| CHSEP_512 |
0x1 |
512 separated |
| CHSEP_8K |
0x5 |
8k separated |
|
[15:11] RO |
PFN
Physical Function Number. This field provides information regarding the DMA register and physical function mapping.
Reset: hex:0x00;
|
[10:08] RO |
BARN
Bar Number. This field provides information regarding the DMA register and BAR number mapping.
Reset: hex:0x4;
|
[07:03] RO |
RSVDP_3
Reserved for future use.
Reset: hex:0x00;
|
[02:00] RO |
MAP_FORMAT
Defines the register map format and features to be one of the following values: Other values are reserved.
Reset: hex:0x7;
| Valid Values |
| Name | Value(s) | Description |
| EDMA_LEGACY_PL |
0x0 |
Legacy DMA register map accessed by the port-logic registers |
| EDMA_LEGACY_UNROLL |
0x1 |
Legacy DMA register map, mapped to a PF/BAR |
| HDMA_COMPATIBILITY_MODE |
0x5 |
HDMA compatibility mode (CC_LEGACY_DMA_MAP =1) register map, mapped to a PF/BAR |
| HDMA_COMPATIBILITY_PL |
0x4 |
HDMA/DMA compatibility (CC_LEGACY_DMA_MAP =1) register map without access through the Wire |
| HDMA_NATIVE |
0x7 |
HDMA native (CC_LEGACY_DMA_MAP =0) register map, mapped to a PF/BAR |
| HDMA_NATIVE_PL |
0x6 |
HDMA native (CC_LEGACY_DMA_MAP =0) register map without access through the Wire |
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+0x000002c8 Register(32 bit) VSECDMA_NUM_CHAN_OFF
Number of Implemented Channels Register.
This register specifies the number of read and write channels implemented.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002c8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00020002 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
| Name |
RSVDP_26 |
NUM_DMA_RD_CHAN |
RSVDP_10 |
NUM_DMA_WR_CHAN |
| Access |
RO |
RO |
RO |
RO |
[31:26] RO |
RSVDP_26
Reserved for future use.
Reset: hex:0x00;
|
[25:16] RO |
NUM_DMA_RD_CHAN
This field provides information regarding the number of implemented read channels. It reports the value of CC_NUM_DMA_RD_CHAN parameter.
Reset: hex:0x002;
|
[15:10] RO |
RSVDP_10
Reserved for future use.
Reset: hex:0x00;
|
[09:00] RO |
NUM_DMA_WR_CHAN
This field provides information regarding the number of implemented write channels. It reports the value of CC_NUM_DMA_WR_CHAN parameter.
Reset: hex:0x002;
|
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+0x000002cc Register(32 bit) VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF
DMA Register Map Start Address Offset Low Register.
This register specifies the lower 32 bits of the offset of the start address of the DMA register map.
Applicable only if MAP_FORMAT >0, that is, all map formats other than EDMA_LEGACY_PL.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002cc at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UNROLL_ADDR_OFFSET_LOW |
| Access |
RO |
[31:00] RO |
UNROLL_ADDR_OFFSET_LOW
BAR address offset, 32-bit LSB.
Reset: hex:0x00000000;
|
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+0x000002d0 Register(32 bit) VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF
DMA Register Map Start Address Offset High Register.
This register specifies the upper 32 bits of the offset of the start address of the DMA register map.
Applicable only if MAP_FORMAT >0, that is, all map formats other than EDMA_LEGACY_PL.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010002d0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UNROLL_ADDR_OFFSET_HIGH |
| Access |
RO |
[31:00] RO |
UNROLL_ADDR_OFFSET_HIGH
BAR address offset, 32-bit MSB.
Reset: hex:0x00000000;
|
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+0x00000700 Register(32 bit) ACK_LATENCY_TIMER_OFF
Ack Latency Timer and Replay Timer Register.
This register holds the ack latency timer limit and replay timer limit values.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000700 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x06110205 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
| Name |
REPLAY_TIME_LIMIT |
ROUND_TRIP_LATENCY_TIME_LIMIT |
| Access |
RW/V |
RW/V |
[31:16] RW/V |
REPLAY_TIME_LIMIT
Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more information, see "Transmit Replay" in the Databook. - You can modify the effective timer limit through the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. - After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4, 3-5, and 3-6 of the PCI Express Base Specification. - If there is a change in the payload size or link speed, the controller overrides any value that you have written to this register field, and resets the field back to the specification-defined value. The controller does not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.
TDISP Prot :WDB
Reset: hex:0x0611;
|
[15:00] RW/V |
ROUND_TRIP_LATENCY_TIME_LIMIT
Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more information, see "ACK/NAK Scheduling" in the Databook. - You can modify the effective timer limit through the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. - After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCI Express Base Specification. - The limit must reflect the round trip latency from requester to completer. - If there is a change in the payload size or link width, the controller overrides any value that you have written to this register field, and resets the field back to the specification-defined value. The controller does not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.
TDISP Prot :WDB
Reset: hex:0x0205;
|
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+0x00000704 Register(32 bit) VENDOR_SPEC_DLLP_OFF
Vendor Specific DLLP Register.
This register holds the vendor specific DLLP.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000704 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0xffffffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
VENDOR_SPEC_DLLP |
| Access |
RW |
[31:00] RW |
VENDOR_SPEC_DLLP
Vendor Specific DLLP Register. You can use this register to send a specific PCI Express DLLP. Your application can write 8-bit DLLP Type and 24-bit Payload data into this register, and set the VENDOR_SPECIFIC_DLLP_REQ field of the PORT_LINK_CTRL_OFF, to send the DLLP. - Bits[7:0]: DLLP Type - Bits[31:8]: Vendor Defined Payload (24 bits)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0xffffffff;
| Valid Values |
| Name | Value(s) | Description |
| MAX |
0x0ffffffff |
Max value |
| ZERO |
0x0 |
Zero value |
|
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+0x00000708 Register(32 bit) PORT_FORCE_OFF
Port Force Link Register.
This register can be used for testing and debuggong the link.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000708 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00800004 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
| Name |
RSVDP_24 |
DO_DESKEW_FOR_SRIS |
SUPPORT_PART_LANES_RXEI_EXIT |
LINK_STATE |
FORCE_EN |
RSVDP_12 |
FORCED_LTSSM |
LINK_NUM |
| Access |
RO |
RW |
RW |
RW |
WS/V |
RO |
RW |
RW |
[31:24] RO |
RSVDP_24
Reserved for future use.
Reset: hex:0x00;
|
[23:23] RW |
DO_DESKEW_FOR_SRIS
Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, EIEOS to Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS is set to '1'. Always set to '1' for flit mode enabled.
Note: This register field is sticky.
Reset: hex:0x1;
|
[22:22] RW |
SUPPORT_PART_LANES_RXEI_EXIT
Support LTSSM transition from Polling.Active to Polling.Config based on Rx 8 TSs on any lanes which are Rx EI exit too from base spec after 24ms timeout. This prevents some lanes detected but not Rx EI exit and LTSSM cannot move to Polling.Config. You must set the parameter CX_AUTO_LANE_FLIP_CTRL_EN true for the auto lanes reversal.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SUPPORT |
0x1 |
Any lanes receives 8 consecutive TS OSs, LTSSM moves from Polling.Active to Polling.Config. If all lanes do not receive 8 consecutive TS OSs and any predetermined lanes are still on Rx ElecIdle, LTSSM moves from Polling.Active to Polling.Compliance. |
| UNSUPPORT |
0x0 |
Any lanes receives 8 consecutive TS OS and all predetermined lanes have Rx ElecIdle exit, LTSSM moves from Polling.Active to Polling.Config. This is legacy mode from Base Spec. Any predetermined lanes are still on Rx ElecIdle, LTSSM moves from Polling.Active to Polling.Compliance. |
|
[21:16] RW |
LINK_STATE
Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:15] WS/V |
FORCE_EN
Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced Link Command field. This is a self-clearing register field. Reading from this register field always returns a '0'.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[14:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x0;
|
[11:08] RW |
FORCED_LTSSM
Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.
Note: This register field is sticky.
Reset: hex:0x0;
|
[07:00] RW |
LINK_NUM
Link Number. Not used for endpoint.
Note: This register field is sticky.
Reset: hex:0x04;
|
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+0x0000070c Register(32 bit) ACK_F_ASPM_CTRL_OFF
Ack Frequency and L0-L1 ASPM Control Register.
This register is used to control ack frequency and L0-L1 ASPM behaviour.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100070c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x9bffff00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ASPM_L1_TIMER_ENABLE |
ENTER_ASPM |
L1_ENTRANCE_LATENCY |
L0S_ENTRANCE_LATENCY |
COMMON_CLK_N_FTS |
ACK_N_FTS |
ACK_FREQ |
| Access |
RW |
WS/V |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
ASPM_L1_TIMER_ENABLE
ASPM L1 Timer Enable. This register controls the behaviour of the controller ASPM L1 Entry Timer.
Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
PM controller will initiate entry into L1 as soon as all the L1 idle conditions are bypassed. This setting is only recommended when the application implements its own timers. |
| ENABLE |
0x1 |
PM controller starts the ASPM L1 timer whenever all the L1 idle conditions are met. This is the default recommended behavior |
|
[30:30] WS/V |
ENTER_ASPM
ASPM L1 Entry Control.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| IDLE_TO_L1 |
0x1 |
Controller enters ASPM L1 after a period in which it has been idle. |
| L0S_TO_L1 |
0x0 |
Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. |
|
[29:27] RW |
L1_ENTRANCE_LATENCY
L1 Entrance Latency. Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.
Note: This register field is sticky.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| _16_US |
0x4 |
16 us |
| _32_US |
0x5 |
32 us |
| _4_US |
0x2 |
4 us |
| _64US_ |
0x7 |
64 us |
| _64_US |
0x6 |
64Us |
| _8_US |
0x3 |
8 us |
| _1_US |
0x0 |
1 us |
| _2_US |
0x1 |
2 us |
|
[26:24] RW |
L0S_ENTRANCE_LATENCY
L0s Entrance Latency.
Note: This register field is sticky.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| _3_US |
0x2 |
3 us |
| _4_US |
0x3 |
4 us |
| _5_US |
0x4 |
5 us |
| _6_US |
0x5 |
6 us |
| _7US_ |
0x7 |
7 us |
| _7_US |
0x6 |
7 US |
| _1_US |
0x0 |
1 us |
| _2_US |
0x1 |
2 us |
|
[23:16] RW |
COMMON_CLK_N_FTS
Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence(N_FTS) ordered sets to be transmitted when transitioning from L0s to L0.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0xff;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ff |
The maximum number of FTS ordered-sets that a component can request is 255. |
| ZERO |
0x0 |
The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. |
|
[15:08] RW |
ACK_N_FTS
The number of Fast Training Sequence(N_FTS) ordered sets to be transmitted when transitioning from L0s to L0.
Note: This register field is sticky.
Reset: hex:0xff;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ff |
The maximum number of FTS ordered-sets that a component can request is 255. |
| ZERO |
0x0 |
The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. |
|
[07:00] RW |
ACK_FREQ
Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK request for every TLP that it receives. The controller waits until the ACK Latency Timer expires, then converts the current low-priority ACK request to a high-priority ACK request and schedules the DLLP for transmission to the remote link partner. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs if the ACK Latency Timer expires, but never later. For a typical system, you do not have to modify the default setting. For more information, see "ACK/NAK Scheduling" in the Databook.
Note: This register field is sticky.
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ff |
Any value between 1 and 255 indicates that the controller will schedule a high-priority ACK after receiving the specified number of TLPs. |
| MIN_VAL |
0x0 |
The value '0' indicates that this Ack Frequency Counter feature is turned off. |
|
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+0x00000710 Register(32 bit) PORT_LINK_CTRL_OFF
Port Link Control Register.
Using this register you can control the port link behaviour.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000710 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00030120 |
|
|
Unaffected |
0x00c00000 |
|
|
Undefined |
0x00c00000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_28 |
TRANSMIT_LANE_REVERSALE_ENABLE |
EXTENDED_SYNCH |
CORRUPT_LCRC_ENABLE |
BEACON_ENABLE |
- |
LINK_CAPABLE |
RSVDP_12 |
LINK_RATE |
FAST_LINK_MODE |
LINK_DISABLE |
DLL_LINK_EN |
RSVDP_4 |
RESET_ASSERT |
LOOPBACK_ENABLE |
SCRAMBLE_DISABLE |
VENDOR_SPECIFIC_DLLP_REQ |
| Access |
RO |
RW |
RW |
RW |
RW |
- |
RW |
RO |
RW |
RW |
RW |
RW |
RO |
RW |
RW |
RW |
RW/1C/V |
[31:28] RO |
RSVDP_28
Reserved for future use.
Reset: hex:0x0;
|
[27:27] RW |
TRANSMIT_LANE_REVERSALE_ENABLE
TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[26:26] RW |
EXTENDED_SYNCH
EXTENDED_SYNCH is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[25:25] RW |
CORRUPT_LCRC_ENABLE
CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[24:24] RW |
BEACON_ENABLE
BEACON_ENABLE is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[21:16] RW |
LINK_CAPABLE
Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment".
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x03;
| Valid Values |
| Name | Value(s) | Description |
| X16 |
0x1f |
x16 |
| X2 |
0x3 |
x2 |
| X32 |
0x3f |
x32 (not supported) |
| X4 |
0x7 |
x4 |
| X8 |
0x0f |
x8 |
| X1 |
0x1 |
x1 |
|
[15:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x0;
|
[11:08] RW |
LINK_RATE
LINK_RATE is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x1;
|
[07:07] RW |
FAST_LINK_MODE
Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. - The default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF register. - Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'. For more information, see the "Fast Link Simulation Mode" section in the "Integrating the Controller with the PHY or Application RTL or Verification IP" chapter of the User Guide.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[06:06] RW |
LINK_DISABLE
LINK_DISABLE is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[05:05] RW |
DLL_LINK_EN
DLL Link Enable.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
The controller does not transmit InitFC DLLPs and does not establish a link. |
| ENABLE |
0x1 |
Enables link initialization. |
|
[04:04] RO |
RSVDP_4
Reserved for future use.
Reset: hex:0x0;
|
[03:03] RW |
RESET_ASSERT
Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
Clear |
| SET |
0x1 |
Set |
|
[02:02] RW |
LOOPBACK_ENABLE
Loopback Enable. Turns on loopback. For more information, see "Loopback" in the Databook.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[01:01] RW |
SCRAMBLE_DISABLE
Scramble Disable. Turns off data scrambling.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[00:00] RW/1C/V |
VENDOR_SPECIFIC_DLLP_REQ
Vendor Specific DLLP Request.
Reading from this self-clearing register field always returns a '0'.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
This is a self clearing register |
| SET |
0x1 |
When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF |
|
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+0x00000714 Register(32 bit) LANE_SKEW_OFF
Lane Skew Register.
This register is used to control the lane skew behaviour.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000714 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x08000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DISABLE_LANE_TO_LANE_DESKEW |
IMPLEMENT_NUM_LANES |
ELASTIC_BUFFER_MODE |
ACK_NAK_DISABLE |
FLOW_CTRL_DISABLE |
DRIFT_BUFFER_DESKEW_ENABLE |
INSERT_LANE_SKEW |
| Access |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
DISABLE_LANE_TO_LANE_DESKEW
Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:27] RW |
IMPLEMENT_NUM_LANES
Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. The number of lanes to be used when in Loopback Master. The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field. The controller will transition from Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field.
Note: This register field is sticky.
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| _16_LANE |
0x0f |
16 lanes |
| _1_LANE |
0x0 |
1 lane |
| _2_LANE |
0x1 |
2 lanes |
| _4_LANE |
0x3 |
4 lanes |
| _8_LANE |
0x7 |
8 lanes |
|
[26:26] RW |
ELASTIC_BUFFER_MODE
Selects Elasticity Buffer operating mode:
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| EMPTY |
0x1 |
Nominal Empty Buffer Mode |
| HALF_FULL |
0x0 |
Nominal Half Full Buffer mode |
|
[25:25] RW |
ACK_NAK_DISABLE
Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[24:24] RW |
FLOW_CTRL_DISABLE
Flow Control Disable. Prevents the controller from sending FC DLLPs.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
DRIFT_BUFFER_DESKEW_ENABLE
DRIFT_BUFFER_DESKEW_ENABLE is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[22:00] RW |
INSERT_LANE_SKEW
INSERT_LANE_SKEW is an internally reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x000000;
| Valid Values |
| Name | Value(s) | Description |
| MAX |
0x7f |
Max value |
| MIN |
0x0 |
Zero value |
|
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+0x00000718 Register(32 bit) TIMER_CTRL_MAX_FUNC_NUM_OFF
Timer Control and Max Function Number Register.
This register holds the ack frequency, latency, replay, fast link scaling timers,
and max function number values.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000718 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x60018000 |
|
|
Unaffected |
0x0007c000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_31 |
FAST_LINK_SCALING_FACTOR |
UPDATE_FREQ_TIMER |
TIMER_MOD_ACK_NAK |
TIMER_MOD_REPLAY_TIMER |
RSVDP_8 |
MAX_FUNC_NUM |
| Access |
RO |
RW |
RW |
RW |
RW/V |
RO |
RW |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:29] RW |
FAST_LINK_SCALING_FACTOR
Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| SF_1024 |
0x0 |
Scaling Factor is 1024 (1ms is 1us). When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, 2ms timer is 4us and 3ms timer is 6us. |
| SF_16 |
0x3 |
Scaling Factor is 16 (1ms is 64us) |
| SF_256 |
0x1 |
Scaling Factor is 256 (1ms is 4us) |
| SF_64 |
0x2 |
Scaling Factor is 64 (1ms is 16us) |
|
[28:24] RW |
UPDATE_FREQ_TIMER
UPDATE_FREQ_TIMER is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x00;
|
[23:19] RW |
TIMER_MOD_ACK_NAK
Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more information, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[18:14] RW/V |
TIMER_MOD_REPLAY_TIMER
Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification to the timer limit. For more information, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x06;
|
[13:08] RO |
RSVDP_8
Reserved for future use.
Reset: hex:0x00;
|
[07:00] RW |
MAX_FUNC_NUM
Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| MAX |
0x0ff |
Max value |
| MIN |
0x0 |
Zero value |
|
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+0x0000071c Register(32 bit) SYMBOL_TIMER_FILTER_1_OFF
Symbol Timer Register and Filter Mask 1 Register.
The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more information, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100071c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00080140 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MASK_RADM_1 |
DISABLE_FC_WD_TIMER |
EIDLE_TIMER |
SKP_INT_VAL |
| Access |
RW |
RW |
RW |
RW |
[31:16] RW |
MASK_RADM_1
Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more information, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.
31: CX_FLT_MASK_RC_CFG_DISCARD - 0x0: For RADM RC filter to not allow CFG transaction being received - 0x1: For RADM RC filter to allow CFG transaction being received 30: CX_FLT_MASK_RC_IO_DISCARD - 0x0: For RADM RC filter to not allow IO transaction being received - 0x1: For RADM RC filter to allow IO transaction being received 29: CX_FLT_MASK_MSG_DROP - 0x0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 0x1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is '0' (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 (or AXI bridge manager), as they are too big for the SII. 28: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0x0: Discard completions with ECRC errors - 0x1: Allow completions with ECRC errors to be passed up - Reserved field for SW. 27: CX_FLT_MASK_ECRC_DISCARD - 0x0: Discard TLPs with ECRC errors - 0x1: Allow TLPs with ECRC errors to be passed up 26: CX_FLT_MASK_CPL_LEN_MATCH - 0x0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 0x1: Mask length match for completions 25: CX_FLT_MASK_CPL_ATTR_MATCH - 0x0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 0x1: Mask attribute match for completions 24: CX_FLT_MASK_CPL_TC_MATCH - 0x0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 0x1: Mask Traffic Class match for completions 23: CX_FLT_MASK_CPL_FUNC_MATCH - 0x0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 0x1: Mask function match for completions 22: CX_FLT_MASK_CPL_REQID_MATCH - 0x0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 0x1: Mask Req. Id match for completions 21: CX_FLT_MASK_CPL_TAGERR_MATCH - 0x0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 0x1: Mask Tag Error Rules for completions 20: CX_FLT_MASK_LOCKED_RD_AS_UR - 0x0: Treat locked Read TLPs as UR for EP; Supported for RC - 0x1: Treat locked Read TLPs as Supported for EP; UR for RC 19: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0x0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 0x1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number. - When CX_IDE_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests when those are received on a Selective Stream as indicated by the IDE Core and only if they match an implemented function. 18: CX_FLT_MASK_UR_OUTSIDE_BAR - 0x0: Treat out-of-bar TLPs as UR - 0x1: Do not treat out-of-bar TLPs as UR 17: CX_FLT_MASK_UR_POIS - 0x0: Treat poisoned request TLPs as UR - 0x1: Do not treat poisoned request TLPs as UR - The native controller always passes poisoned completions to your application except when you are using the DMA read channel. - For Multistream Architecture, When CX_FLT_MASK_UR_POIS=1, TLP is sent to TRGT1 as poisoned TLP, in this case error must be logged by your application. 16: CX_FLT_MASK_UR_FUNC_MISMATCH - 0x0: Treat Function MisMatched TLPs as UR - 0x1: Do not treat Function MisMatched TLPs as UR - CX_FLT_MASK_UR_FUNC_MISMATCH is not allowed to be set unless CONFIG_LIMIT_REG =0 and TARGET_ABOVE_CONFIG_LIMIT_REG =2 in MISC_CONTROL_1_OFF register or CFG_TLP_BYPASS_EN_REG =1 and TARGET_ABOVE_CONFIG_LIMIT_REG =2 in MISC_CONTROL_1_OFF register.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0008;
| Valid Values |
| Name | Value(s) | Description |
| Maxvalue |
0x0ffff |
Max value |
| Minvalue |
0x0 |
Zero value |
|
[15:15] RW |
DISABLE_FC_WD_TIMER
Disable FC Watchdog Timer.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[14:11] RW |
EIDLE_TIMER
EIDLE_TIMER is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[10:00] RW |
SKP_INT_VAL
SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. The controller waits the number of symbol times in this register plus 1, between transmitting SKP ordered sets. Your application must program this register accordingly.
For example, if 1536 were programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP ordered sets once every 1537 symbol times.
The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick =two symbol times in this case).
Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x140;
|
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+0x00000720 Register(32 bit) FILTER_MASK_2_OFF
Filter Mask 2 Register.
This register modifies the RADM filtering and error handling rules. For more information, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000720 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MASK_RADM_2 |
| Access |
RW |
[31:00] RW |
MASK_RADM_2
Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more information, see the "Receive Filtering" in the Databook. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.
31:17: Reserved 16: CX_FLT_MASK_RP_TDISP_EN_TBIT_SET_NOT_LOCK_SEL_STR - 0x0: Drop Request if IDE-Tbit==1 while RMEDA_CTL1.TDISP_EN==1 but it is not on locked selective stream. Valid only for Root Ports when CC_RP_TDISP is enabled - 0x1: Do not drop Request if IDE-Tbit==1 while RMEDA_CTL1.TDISP_EN==1 but it is not on locked selective stream. Valid only for Root Ports when CC_RP_TDISP is enabled 15: CX_FLT_MASK_RP_TDISP_EN_CLEAR_TBIT_SET - 0x0: Drop Request if IDE-Tbit==1 while RMEDA_CTL1.TDISP_EN==0. Valid only for Root Ports when CC_RP_TDISP is enabled - 0x1: Do not drop Request if IDE-Tbit==1 while RMEDA_CTL1.TDISP_EN==0. Valid only for Root Ports when CC_RP_TDISP is enabled
14: CX_FLT_MASK_RCB_CHECK "The Read Completion Boundary (RCB) determines the naturally aligned address boundaries on which a Completer is permitted to break up the response for a single Read Request into multiple Completions. If the received completion violates this rules the controller handles the Completion as a malformed TLP. To disable this filtering rule the user can set the mask field, CX_FLT_MASK_RCB_CHECK, to 1." - 0x0: Disable masking of CPL RCB check. - 0x1: Enable masking of CPL RCB check.
13: CX_FLT_MASK_TDISP_DROP_CPL_NOT_RUN - 0x0: Drop CPL for Memory Reads received while TEE not in RUN for TDISP devices - 0x1: Do not drop CPL for Memory Reads while TEE not in RUN for TDISP devices 12: CX_FLT_MASK_TDISP_DROP_ATS_CPL_TBIT - 0x0: Drop CPL for ATS Translation Requests when Tbit=0 for TDISP devices - 0x1: Do not drop CPL for ATS Translation Requests when Tbit=0 for TDISP devices 11: CX_FLT_UNMASK_ATOMIC_SPECIFIC_RULES - 0x0: Lower Address is checked for Cpls related to AtomicOps Requests. - 0x1: Lower Address is not checked for Cpls related to AtomicOps Requests. 10: CX_FLT_UNMASK_ATS_SPECIFIC_RULES - 0x0: Cpls for ATS Requests are processed as MemRd-related Cpl. - 0x1: Lower Address is not checked for Cpls related to ATS Requests. An ATS-related Cpl completes the request if it has a Byte Count that is equal to four times the Length field. 9: CX_FLT_MASK_CPL_IN_LUT_CHECK - 0x0: Disable masking of checking if the tag of CPL is registered in LUT - 0x1: Enable masking of checking if the tag of CPL is registered in LUT 8: CX_FLT_MASK_POIS_ERROR_REPORTING - 0x0: Disable masking of error reporting for Poisoned TLPs - 0x1: Enable masking of error reporting for Poisoned TLPs - This bit is not applicable for Multistream Architecture. 7: CX_FLT_MASK_PRS_DROP - 0x0: Allow PRS message to pass through - 0x1: Drop PRS Messages silently - This bit is ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the SYMBOL_TIMER_FILTER_1_OFF register is set to '1'. 6: CX_FLT_UNMASK_TD - 0x0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE - 0x1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE 5: CX_FLT_UNMASK_UR_POIS_TRGT0 - 0x0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 0x1: Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination 4: CX_FLT_MASK_LN_VENMSG1_DROP - 0x0: Allow LN message to pass through - 0x1: Drop LN Messages silently 3: CX_FLT_MASK_HANDLE_FLUSH - 0x0: Disable controller Filter to handle flush request - 0x1: Enable controller Filter to handle flush request 2: CX_FLT_MASK_DABORT_4UCPL - 0x0: Enable DLLP abort for unexpected completion - 0x1: Do not enable DLLP abort for unexpected completion 1: CX_FLT_MASK_VENMSG1_DROP - 0x0: Vendor MSG Type 1 dropped silently - 0x1: Vendor MSG Type 1 not dropped 0: CX_FLT_MASK_VENMSG0_DROP - 0x0: Vendor MSG Type 0 dropped with UR error reporting - 0x1: Vendor MSG Type 0 not dropped
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Maximumvalue |
0x0ffffffff |
Max value |
| Minimunvalue |
0x0 |
Zero value |
|
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+0x00000728 Register(32 bit) PL_DEBUG0_OFF
Debug Register 0.
This register holds cxpl_debug_info[31:0].
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000728 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000000 |
|
|
Unaffected |
0xffffffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DEB_REG_0 |
| Access |
RO/V |
[31:00] RO/V |
DEB_REG_0
The value on cxpl_debug_info[31:0].
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| MAX |
0x0ffffffff |
Max value. |
| ZERO |
0x0 |
Zero value. |
|
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+0x0000072c Register(32 bit) PL_DEBUG1_OFF
Debug Register 1.
This register holds cxpl_debug_info[63:32].
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100072c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000000 |
|
|
Unaffected |
0xffffffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DEB_REG_1 |
| Access |
RO/V |
[31:00] RO/V |
DEB_REG_1
The value on cxpl_debug_info[63:32].
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| MAX |
0x0ffffffff |
Max value. |
| ZERO |
0x0 |
Zero value. |
|
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+0x00000730 Register(32 bit) TX_P_FC_CREDIT_STATUS_OFF
Transmit Posted FC Credit Status.
This register provides transmit posted FC credit status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000730 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_TX_P_FC_CREDIT_STATUS |
TX_P_HEADER_FC_CREDIT |
TX_P_DATA_FC_CREDIT |
| Access |
RO |
RO/V |
RO/V |
[31:28] RO |
RSVDP_TX_P_FC_CREDIT_STATUS
Reserved for future use.
Reset: hex:0x0;
|
[27:16] RO/V |
TX_P_HEADER_FC_CREDIT
Transmit Posted Header FC Credits. - The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. - Default value depends on the number of advertised credits for header and data - Scaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF]. - No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
Reset: hex:0x000;
|
[15:00] RO/V |
TX_P_DATA_FC_CREDIT
Transmit Posted Data FC Credits. - The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. - Default value depends on the number of advertised credits for header and data - Scaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF]. - No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
Reset: hex:0x0000;
|
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+0x00000734 Register(32 bit) TX_NP_FC_CREDIT_STATUS_OFF
Transmit Non-Posted FC Credit Status.
This register provides the transmit Non-Posted FC credit status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000734 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_TX_NP_FC_CREDIT_STATUS |
TX_NP_HEADER_FC_CREDIT |
TX_NP_DATA_FC_CREDIT |
| Access |
RO |
RO/V |
RO/V |
[31:28] RO |
RSVDP_TX_NP_FC_CREDIT_STATUS
Reserved for future use.
Reset: hex:0x0;
|
[27:16] RO/V |
TX_NP_HEADER_FC_CREDIT
Transmit Non-Posted Header FC Credits. - The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. - Default value depends on the number of advertised credits for header and data - Scaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF]. - No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
Reset: hex:0x000;
|
[15:00] RO/V |
TX_NP_DATA_FC_CREDIT
Transmit Non-Posted Data FC Credits. - The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. - Default value depends on the number of advertised credits for header and data - Scaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF]. - No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
Reset: hex:0x0000;
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+0x00000738 Register(32 bit) TX_CPL_FC_CREDIT_STATUS_OFF
Transmit Completion FC Credit Status
This register provides transmit completion FC credit status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000738 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_TX_CPL_FC_CREDIT_STATUS |
TX_CPL_HEADER_FC_CREDIT |
TX_CPL_DATA_FC_CREDIT |
| Access |
RO |
RO/V |
RO/V |
[31:28] RO |
RSVDP_TX_CPL_FC_CREDIT_STATUS
Reserved for future use.
Reset: hex:0x0;
|
[27:16] RO/V |
TX_CPL_HEADER_FC_CREDIT
Transmit Completion Header FC Credits. - The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. - Default value depends on the number of advertised credits for header and data - Scaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF]. - No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
Reset: hex:0x000;
|
[15:00] RO/V |
TX_CPL_DATA_FC_CREDIT
Transmit Completion Data FC Credits. - The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. - Default value depends on the number of advertised credits for header and data - Scaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF]. - No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
Reset: hex:0x0000;
|
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+0x0000073c Register(32 bit) QUEUE_STATUS_OFF
Queue Status.
This register provides the queue status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100073c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x0000c000 |
|
|
Undefined |
0x0000c000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
TIMER_MOD_FLOW_CONTROL_EN |
RSVDP_29 |
TIMER_MOD_FLOW_CONTROL |
- |
RX_SERIALIZATION_Q_NON_EMPTY |
RSVDP_4 |
RX_QUEUE_OVERFLOW |
RX_QUEUE_NON_EMPTY |
TX_RETRY_BUFFER_NE |
RX_TLP_FC_CREDIT_NON_RETURN |
| Access |
RW |
RO |
RW |
- |
RO/V |
RO |
RW/1C/V |
RO/V |
RO/V |
RO/V |
[31:31] RW |
TIMER_MOD_FLOW_CONTROL_EN
FC Latency Timer Override Enable.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the controller calculates according to the PCIe specification. |
| CLEAR |
0x0 |
Clear |
|
[30:29] RO |
RSVDP_29
Reserved for future use.
Reset: hex:0x0;
|
[28:16] RW |
TIMER_MOD_FLOW_CONTROL
FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the controller calculates according to the PCIe specification. For more information, see "Flow Control" in the Databook.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[13:13] RO/V |
RX_SERIALIZATION_Q_NON_EMPTY
Receive Serialization Queue Not Empty.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates there is data in the serialization queue. |
| CLEAR |
0x0 |
Clear |
|
[12:04] RO |
RSVDP_4
Reserved for future use.
Reset: hex:0x000;
|
[03:03] RW/1C/V |
RX_QUEUE_OVERFLOW
Receive Credit Queue Overflow.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates insufficient buffer space available to write to the P/NP/CPL credit queue. |
| CLEAR |
0x0 |
Clear |
|
[02:02] RO/V |
RX_QUEUE_NON_EMPTY
Receive Credit Queue Not Empty.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates there is data in one or more of the receive buffers. |
| CLEAR |
0x0 |
Clear |
|
[01:01] RO/V |
TX_RETRY_BUFFER_NE
Transmit Retry Buffer Not Empty.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates that there is data in the transmit retry buffer. |
| CLEAR |
0x0 |
Clear |
|
[00:00] RO/V |
RX_TLP_FC_CREDIT_NON_RETURN
Received TLP FC Credits Not Returned.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link. |
| CLEAR |
0x0 |
Clear |
|
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+0x00000740 Register(32 bit) VC_TX_ARBI_1_OFF
VC Transmit Arbitration Register 1.
This register is used for setting the WRR weights for VC0 - VC3.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000740 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000000f |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
| Name |
WRR_WEIGHT_VC_3 |
WRR_WEIGHT_VC_2 |
WRR_WEIGHT_VC_1 |
WRR_WEIGHT_VC_0 |
| Access |
RO |
RO |
RO |
RO |
[31:24] RO |
WRR_WEIGHT_VC_3
WRR Weight for VC3.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x00;
|
[23:16] RO |
WRR_WEIGHT_VC_2
WRR Weight for VC2.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x00;
|
[15:08] RO |
WRR_WEIGHT_VC_1
WRR Weight for VC1.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x00;
|
[07:00] RO |
WRR_WEIGHT_VC_0
WRR Weight for VC0.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x0f;
|
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+0x00000744 Register(32 bit) VC_TX_ARBI_2_OFF
VC Transmit Arbitration Register 2.
This register is used for setting the WRR weights for VC4 - VC7.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000744 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
WRR_WEIGHT_VC_7 |
WRR_WEIGHT_VC_6 |
WRR_WEIGHT_VC_5 |
WRR_WEIGHT_VC_4 |
| Access |
RO |
RO |
RO |
RO |
[31:24] RO |
WRR_WEIGHT_VC_7
WRR Weight for VC7.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x00;
|
[23:16] RO |
WRR_WEIGHT_VC_6
WRR Weight for VC6.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x00;
|
[15:08] RO |
WRR_WEIGHT_VC_5
WRR Weight for VC5.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x00;
|
[07:00] RO |
WRR_WEIGHT_VC_4
WRR Weight for VC4.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R
Reset: hex:0x00;
|
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+0x00000748 Register(32 bit) VC0_P_RX_Q_CTRL_OFF
Segmented-Buffer VC0 Posted Receive Queue Control.
This register controls segmented-buffer VC0 posted receive queue operation.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000748 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x46220130 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
VC_ORDERING_RX_Q |
TLP_TYPE_ORDERING_VC0 |
RESERVED5 |
VC0_P_DATA_SCALE |
VC0_P_HDR_SCALE |
VC0_P_TLP_Q_MODE |
RESERVED4 |
VC0_P_HEADER_CREDIT |
VC0_P_DATA_CREDIT |
| Access |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
VC_ORDERING_RX_Q
VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration:
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ROUND_ROBIN |
0x0 |
Round robin |
| STRICT_ORDERING |
0x1 |
Strict ordering, higher numbered VCs have higher priority |
|
[30:30] RW |
TLP_TYPE_ORDERING_VC0
TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration:
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| PCIE_ORDERING_RULE |
0x1 |
PCIe ordering rules (recommended) |
| STRICT_ORDERING |
0x0 |
Strict ordering: posted, completion, then non-posted |
|
[29:28] RW |
RESERVED5
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[27:26] RW |
VC0_P_DATA_SCALE
VC0 Scale Posted Data Credits.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x3 |
Max value |
|
[25:24] RW |
VC0_P_HDR_SCALE
VC0 Scale Posted Header Credits.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x3 |
Max value |
|
[23:21] RW |
VC0_P_TLP_Q_MODE
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
|
[20:20] RW |
RESERVED4
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[19:12] RW |
VC0_P_HEADER_CREDIT
VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x20;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x0ff |
Max value |
|
[11:00] RW |
VC0_P_DATA_CREDIT
VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x130;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0fff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
|
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+0x0000074c Register(32 bit) VC0_NP_RX_Q_CTRL_OFF
Segmented-Buffer VC0 Non-Posted Receive Queue Control.
This register controls the segmented-buffer VC0 non-posted receive queue operation.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100074c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x06220020 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
| Name |
RESERVED7 |
VC0_NP_DATA_SCALE |
VC0_NP_HDR_SCALE |
VC0_NP_TLP_Q_MODE |
RESERVED6 |
VC0_NP_HEADER_CREDIT |
VC0_NP_DATA_CREDIT |
| Access |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:28] RW |
RESERVED7
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[27:26] RW |
VC0_NP_DATA_SCALE
VC0 Scale Non-Posted Data Credits.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x3 |
Max value |
|
[25:24] RW |
VC0_NP_HDR_SCALE
VC0 Scale Non-Posted Header Credits.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x3 |
Max value |
|
[23:21] RW |
VC0_NP_TLP_Q_MODE
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
|
[20:20] RW |
RESERVED6
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[19:12] RW |
VC0_NP_HEADER_CREDIT
VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x20;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x0ff |
Max value |
|
[11:00] RW |
VC0_NP_DATA_CREDIT
VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x020;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0fff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
|
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+0x00000750 Register(32 bit) VC0_CPL_RX_Q_CTRL_OFF
Segmented-Buffer VC0 Completion Receive Queue Control.
This register controls the segmented-buffer VC0 completion receive queue operation.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000750 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x06200000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RESERVED9 |
VC0_CPL_DATA_SCALE |
VC0_CPL_HDR_SCALE |
VC0_CPL_TLP_Q_MODE |
RESERVED8 |
VC0_CPL_HEADER_CREDIT |
VC0_CPL_DATA_CREDIT |
| Access |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:28] RW |
RESERVED9
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[27:26] RW |
VC0_CPL_DATA_SCALE
VC0 Scale CPL Data Credits.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x3 |
Max value |
|
[25:24] RW |
VC0_CPL_HDR_SCALE
VC0 Scale CPL Header Credits.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x2;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x3 |
Max value |
|
[23:21] RW |
VC0_CPL_TLP_Q_MODE
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
|
[20:20] RW |
RESERVED8
Reserved.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[19:12] RW |
VC0_CPL_HEADER_CREDIT
VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Zero value |
| MAX_VAL |
0x0ff |
Max value |
|
[11:00] RW |
VC0_CPL_DATA_CREDIT
VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x000;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0fff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
|
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+0x0000080c Register(32 bit) GEN2_CTRL_OFF
Link Width and Speed Change Control Register.
This register controls various functions of the controller related to link training, lane reversal, and equalization.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100080c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x300102ff |
|
|
Unaffected |
0x80000000 |
|
|
Undefined |
0x80000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
- |
FORCE_LANE_FLIP |
TX_MOD_CMPL_PATTERN_FOR_LOOPBACK |
EQ_FOR_LOOPBACK |
LANE_UNDER_TEST |
SELECTABLE_DEEMPH_BIT_MUX |
SELECT_DEEMPH_VAR_MUX |
GEN1_EI_INFERENCE |
SEL_DEEMPHASIS |
CONFIG_TX_COMP_RX |
CONFIG_PHY_TX_CHANGE |
DIRECT_SPEED_CHANGE |
AUTO_LANE_FLIP_CTRL_EN |
PRE_DET_LANE |
NUM_OF_LANES |
FAST_TRAINING_SEQ |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW/V |
RW |
RW |
RW |
RW |
[30:30] RW |
FORCE_LANE_FLIP
Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[29:29] RW |
TX_MOD_CMPL_PATTERN_FOR_LOOPBACK
Require Loopback slave to transmit Modified Compliance Pattern in Loopback.Active state at Gen5 rate. The default of this field is the CX_DEFAULT_GEN5_TX_MOD_CMPL_PATTERN_FOR_LOOPBACK configuration paramete
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| ENABLE |
0x1 |
Writing '1' to this field through the DBI instructs the remote Loopback slave to send Modified Compliance Pattern in Gen5 loopback.Active. |
| DISABLE |
0x0 |
Disable |
|
[28:28] RW |
EQ_FOR_LOOPBACK
Perform EQ in Loopback in Gen5 and above data rate. The default of this field is the CX_DEFAULT_GEN5_EQ_FOR_LOOPBACK configuration parameter. Loopback master enters Loopback.Active only because of receiving 2 TS1s with Loopback bit asserted (not the 2ms timeout of Txing Compliance Receive bit) if EQ_FOR_LOOPBACK is set to 1.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| ENABLE |
0x1 |
Writing '1' to this field through the DBI instructs the link to perform Eq in Gen5 or above loopback if both sides support Gen5 or above data rate. |
| DISABLE |
0x0 |
Disable |
|
[27:24] RW |
LANE_UNDER_TEST
The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x1 |
CX_NL |
| MIN_VAL |
0x0 |
Zero |
|
[23:23] RW |
SELECTABLE_DEEMPH_BIT_MUX
The selectable deemphasis bit (Symbol 4 bit 6) of the transmitted TS2 Ordered Sets for DSP in Recovery.RcvrCfg state is muxed between the Selectable De-emphasis field in the Link Control 2 register and the value requested by USP in Recovery.RcvrLock state through Tx TS1s from USP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FROM_LINK_CTRL_2_REG |
0x0 |
The value from the Selectable De-emphasis field in the Link Control 2 register |
| REQUESTED_BY_USP |
0x1 |
The value requested by USP in Recovery.RcvrLock state through Tx TS1s from USP |
|
[22:22] RW |
SELECT_DEEMPH_VAR_MUX
The select_deemphasis variable for DSP on entry to Recovery.RcvrCfg state is muxed between the Selectable De-emphasis field in the Link Control 2 register and the value requested by the Upstream Port in the eight consecutive TS1 Ordered Sets it received.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FROM_LINK_CTRL_2_REG |
0x1 |
The value from the Selectable De-emphasis field in the Link Control 2 register |
| REQUESTED_BY_USP |
0x0 |
The value requested by USP in Recovery.RcvrLock state through Tx TS1s from USP |
|
[21:21] RW |
GEN1_EI_INFERENCE
Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking for a '0' on RxValid. If the PHY fails to de-assert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| RXELECIDLE_TO_INFER |
0x0 |
Use RxElecIdle signal to infer Electrical Idle |
| RXVALID_TO_INFER |
0x1 |
Use RxValid signal to infer Electrical Idle |
|
[20:20] RW |
SEL_DEEMPHASIS
Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| N_3_5DB |
0x1 |
-3.5 dB |
| N_6DB |
0x0 |
-6 dB |
|
[19:19] RW |
CONFIG_TX_COMP_RX
Config Tx Compliance Receive Bit.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). |
| CLEAR |
0x0 |
Clear |
|
[18:18] RW |
CONFIG_PHY_TX_CHANGE
Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FULL_SWING |
0x0 |
Full Swing |
| LOW_SWING |
0x1 |
Low Swing |
|
[17:17] RW/V |
DIRECT_SPEED_CHANGE
Directed Speed Change.
When the speed change occurs, the controller will clear the contents of this field; and a read to this field by your software will return a '0'. To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG.PCIE_CAP_TARGET_LINK_SPEED in the local device - De-assert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to '1', then the speed change is initiated automatically after link up, and the controller clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF.PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. |
| CLEAR |
0x0 |
Clear |
|
[16:16] RW |
AUTO_LANE_FLIP_CTRL_EN
Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more information, see the 'Lane Reversal' appendix in the Databook.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:13] RW |
PRE_DET_LANE
Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| LANE0 |
0x0 |
Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detected |
| LANE1 |
0x1 |
Connect logical Lane0 to physical lane 1 |
| LANE15 |
0x4 |
Connect logical Lane0 to physical lane 15 |
| LANE3 |
0x2 |
Connect logical Lane0 to physical lane 3 |
| LANE7 |
0x3 |
connect logical lane0 to physical lane 7 |
|
[12:08] RW |
NUM_OF_LANES
Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base Specification. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes" in the Databook. For information on upsizing and downsizing the link width, see "Link Establishment" in the Databook.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x02;
| Valid Values |
| Name | Value(s) | Description |
| _1_LANE |
0x1 |
1 lane |
| _2_LANE |
0x2 |
2 lanes |
| _3_LANE |
0x3 |
3 lanes |
|
[07:00] RW |
FAST_TRAINING_SEQ
Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or above link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0xff;
|
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+0x00000810 Register(32 bit) PHY_STATUS_OFF
PHY Status Register.
Memory mapped register from phy_cfg_status GPIO input pins.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000810 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000000 |
|
|
Unaffected |
0xffffffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PHY_STATUS |
| Access |
RO/V |
[31:00] RO/V |
PHY_STATUS
PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband status signalling requirements that you have for your PHY.
Note: This register field is sticky.
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffffffff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
|
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+0x00000814 Register(32 bit) PHY_CONTROL_OFF
PHY Control Register.
Memory mapped register to cfg_phy_control GPIO output pins.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000814 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000041 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
| Name |
PHY_CONTROL |
| Access |
RW |
[31:00] RW |
PHY_CONTROL
PHY Control. Data sent directly to the cfg_phy_control bus. This is a GPIO register driving the values on the static cfg_phy_control output signals, and does not in any way influence controller functionality. It can be used for any static sideband control signaling requirements that you have for your PHY. Usage of this register and the associated GPIO bus is RESERVED when the controller is connected to a Synopsys PHY.
Note: This register field is sticky.
Reset: hex:0x00000041;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffffffff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
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+0x0000081c Register(32 bit) TRGT_MAP_CTRL_OFF
Programmable Target Map Control Register.
This register controls the target map.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100081c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x0000004f |
|
|
Unaffected |
0x00001f80 |
|
|
Undefined |
0x00001f80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
| Name |
TARGET_MAP_RESERVED_21_31 |
TARGET_MAP_INDEX |
TARGET_MAP_RESERVED_13_15 |
- |
TARGET_MAP_ROM |
TARGET_MAP_PF |
| Access |
RO |
RW/V |
RO |
- |
RW/V |
RW/V |
[31:21] RO |
TARGET_MAP_RESERVED_21_31
Reserved.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) TDISP Prot :WP
Reset: hex:0x000;
|
[20:16] RW/V |
TARGET_MAP_INDEX
The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting, any write will affect all register bits. This register can be used to read or re-program the target for function numbers from 0 to 31 only.
TDISP Prot :WP
Reset: hex:0x00;
|
[15:13] RO |
TARGET_MAP_RESERVED_13_15
Reserved.
Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) TDISP Prot :WP
Reset: hex:0x0;
|
[06:06] RW/V |
TARGET_MAP_ROM
Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting, any write will affect all register bits.
TDISP Prot :WP
Reset: hex:0x1;
|
[05:00] RW/V |
TARGET_MAP_PF
Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting, any write will affect all register bits.
TDISP Prot :WP
Reset: hex:0x0f;
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+0x0000088c Register(32 bit) CLOCK_GATING_CTRL_OFF
Clock Gating Control Register.
This register enables you to disable dynamic clock gating. By default dynamic clock gating is on, allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module, DWC_pcie_clk_rst.v, and is initiated by the controllers clock enable signals. The following modules support dynamic clock gating:
- AXI Bridge
- RADM
- CDM
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100088c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000003 |
|
|
Unaffected |
0x00000004 |
|
|
Undefined |
0x00000004 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
1 |
1 |
| Name |
RSVDP_3 |
- |
AXI_CLK_GATING_EN |
RADM_CLK_GATING_EN |
| Access |
RO |
- |
RW |
RW |
[31:03] RO |
RSVDP_3
Reserved for future use.
Reset: hex:0x00000000;
|
[01:01] RW |
AXI_CLK_GATING_EN
AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Manager clock, the AXI Subordinate clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock, mstr_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, mstr_aclk_active, is asserted. For the AXI Subordinate this module provides the gated clock, slv_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, slv_aclk_active, is asserted. If the AXI DBI Slave is enabled (DBI_4SLAVE_POPULATED=1) the module provides the gated clock, dbi_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, dbi_aclk_active, is asserted. The controller de-asserts the clock enable signals when the respective AXI Manager/Subordinate interfaces are idle.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable (default) |
|
[00:00] RW |
RADM_CLK_GATING_EN
RADM Clock Gating Enable. This register, if set, enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock, radm_clk_g, to the RADM and is enabled when the controllers clock enable signal, en_radm_clk_g, is asserted. The RADM clock is a gated version of the controller clock, core_clk. The controller de-asserts en_radm_clk_g when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable (default) |
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+0x00000890 Register(32 bit) GEN3_RELATED_OFF
Gen3 Control Register.
There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to '1' and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000890 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00402000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_26 |
RATE_SHADOW_SEL |
GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE |
USP_SEND_8GT_EQ_TS2_DISABLE |
AUTO_EQ_DISABLE |
RSVDP_19 |
GEN3_DC_BALANCE_DISABLE |
GEN3_DLLP_XMT_DELAY_DISABLE |
GEN3_EQUALIZATION_DISABLE |
GEN3_EQ_PSET_COEF_MAP_MODE_PROG |
RSVDP_14 |
RXEQ_RGRDLESS_RXTS |
RXEQ_PH01_EN |
EQ_REDO |
EQ_EIEOS_CNT |
EQ_PHASE_2_3 |
DISABLE_SCRAMBLER_GEN_3 |
RSVDP_2 |
NO_SEED_VALUE_CHANGE |
GEN3_ZRXDC_NONCOMPL |
| Access |
RO |
RW |
RW |
RW/V |
RW/V |
RO |
RW |
RW |
RW |
RW |
RO |
RW |
RW |
RW |
RW |
RW |
RW |
RO |
RW |
RW |
[31:26] RO |
RSVDP_26
Reserved for future use.
Reset: hex:0x00;
|
[25:24] RW |
RATE_SHADOW_SEL
Rate Shadow Select. This register value decide the Data Rate of shadow register. The following shadow registers are controlled by this register. - GEN3_RELATED_OFF[9] EQ_PHASE_2_3 - GEN3_RELATED_OFF[12] RXEQ_PH01_EN - GEN3_RELATED_OFF[19] RE_EQ_REQUEST_ENABLE - GEN3_RELATED_OFF[21] AUTO_EQ_DISABLE - GEN3_RELATED_OFF[22] USP_SEND_8GT_EQ_TS2_DISABLE - GEN3_EQ_LOCAL_FS_LF_OFF[5:0] GEN3_EQ_LOCAL_LF - GEN3_EQ_LOCAL_FS_LF_OFF[11:6] GEN3_EQ_LOCAL_FS - GEN3_EQ_PSET_COEFF_MAP_0[5:0] GEN3_EQ_PRE_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[11:6] GEN3_EQ_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[17:12] GEN3_EQ_POST_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[20:18] GEN6_EQ_PRE_CURSOR_2_PSET - GEN3_FCOEF_VEC_DEPTH_OFF[4:0] GEN3_FCOEF_MAX_VEC_DEPTH - GEN3_FCOEF_VEC_DEPTH_OFF[11:8] GEN3_FCOEF_ACCESS_VAR - GEN3_FCOEF_LANE1_0_OFF[5:0] GEN3_FCOEF_LANE0_PRE_CURSOR - GEN3_FCOEF_LANE1_0_OFF[11:6] GEN3_FCOEF_LANE0_POST_CURSOR - GEN3_FCOEF_LANE1_0_OFF[14:12] GEN6_FCOEF_LANE0_PRE_CURSOR_2 - GEN3_FCOEF_LANE1_0_OFF[21:16] GEN3_FCOEF_LANE1_PRE_CURSOR - GEN3_FCOEF_LANE1_0_OFF[27:22] GEN3_FCOEF_LANE1_POST_CURSOR - GEN3_FCOEF_LANE1_0_OFF[30:28] GEN6_FCOEF_LANE1_PRE_CURSOR_2 - GEN3_FCOEF_LANE3_2_OFF[5:0] GEN3_FCOEF_LANE2_PRE_CURSOR - GEN3_FCOEF_LANE3_2_OFF[11:6] GEN3_FCOEF_LANE2_POST_CURSOR - GEN3_FCOEF_LANE3_2_OFF[14:12] GEN6_FCOEF_LANE2_PRE_CURSOR_2 - GEN3_FCOEF_LANE3_2_OFF[21:16] GEN3_FCOEF_LANE3_PRE_CURSOR - GEN3_FCOEF_LANE3_2_OFF[27:22] GEN3_FCOEF_LANE3_POST_CURSOR - GEN3_FCOEF_LANE3_2_OFF[30:28] GEN6_FCOEF_LANE3_PRE_CURSOR_2 - GEN3_FCOEF_LANE5_4_OFF[5:0] GEN3_FCOEF_LANE4_PRE_CURSOR - GEN3_FCOEF_LANE5_4_OFF[11:6] GEN3_FCOEF_LANE4_POST_CURSOR - GEN3_FCOEF_LANE5_4_OFF[14:12] GEN6_FCOEF_LANE4_PRE_CURSOR_2 - GEN3_FCOEF_LANE5_4_OFF[21:16] GEN3_FCOEF_LANE5_PRE_CURSOR - GEN3_FCOEF_LANE5_4_OFF[27:22] GEN3_FCOEF_LANE5_POST_CURSOR - GEN3_FCOEF_LANE5_4_OFF[30:28] GEN6_FCOEF_LANE5_PRE_CURSOR_2 - GEN3_FCOEF_LANE7_6_OFF[5:0] GEN3_FCOEF_LANE6_PRE_CURSOR - GEN3_FCOEF_LANE7_6_OFF[11:6] GEN3_FCOEF_LANE6_POST_CURSOR - GEN3_FCOEF_LANE7_6_OFF[14:12] GEN6_FCOEF_LANE6_PRE_CURSOR_2 - GEN3_FCOEF_LANE7_6_OFF[21:16] GEN3_FCOEF_LANE7_PRE_CURSOR - GEN3_FCOEF_LANE7_6_OFF[27:22] GEN3_FCOEF_LANE7_POST_CURSOR - GEN3_FCOEF_LANE7_6_OFF[30:28] GEN6_FCOEF_LANE7_PRE_CURSOR_2 - GEN3_FCOEF_LANE9_8_OFF[5:0] GEN3_FCOEF_LANE8_PRE_CURSOR - GEN3_FCOEF_LANE9_8_OFF[11:6] GEN3_FCOEF_LANE8_POST_CURSOR - GEN3_FCOEF_LANE9_8_OFF[14:12] GEN6_FCOEF_LANE8_PRE_CURSOR_2 - GEN3_FCOEF_LANE9_8_OFF[21:16] GEN3_FCOEF_LANE9_PRE_CURSOR - GEN3_FCOEF_LANE9_8_OFF[27:22] GEN3_FCOEF_LANE9_POST_CURSOR - GEN3_FCOEF_LANE9_8_OFF[30:28] GEN6_FCOEF_LANE9_PRE_CURSOR_2 - GEN3_FCOEF_LANE11_10_OFF[5:0] GEN3_FCOEF_LANE10_PRE_CURSOR - GEN3_FCOEF_LANE11_10_OFF[11:6] GEN3_FCOEF_LANE10_POST_CURSOR - GEN3_FCOEF_LANE11_10_OFF[14:12] GEN6_FCOEF_LANE10_PRE_CURSOR_2 - GEN3_FCOEF_LANE11_10_OFF[21:16] GEN3_FCOEF_LANE11_PRE_CURSOR - GEN3_FCOEF_LANE11_10_OFF[27:22] GEN3_FCOEF_LANE11_POST_CURSOR - GEN3_FCOEF_LANE11_10_OFF[30:28] GEN6_FCOEF_LANE11_PRE_CURSOR_2 - GEN3_FCOEF_LANE13_12_OFF[5:0] GEN3_FCOEF_LANE12_PRE_CURSOR - GEN3_FCOEF_LANE13_12_OFF[11:6] GEN3_FCOEF_LANE12_POST_CURSOR - GEN3_FCOEF_LANE13_12_OFF[14:12] GEN6_FCOEF_LANE12_PRE_CURSOR_2 - GEN3_FCOEF_LANE13_12_OFF[21:16] GEN3_FCOEF_LANE13_PRE_CURSOR - GEN3_FCOEF_LANE13_12_OFF[27:22] GEN3_FCOEF_LANE13_POST_CURSOR - GEN3_FCOEF_LANE13_12_OFF[30:28] GEN6_FCOEF_LANE13_PRE_CURSOR_2 - GEN3_FCOEF_LANE15_14_OFF[5:0] GEN3_FCOEF_LANE14_PRE_CURSOR - GEN3_FCOEF_LANE15_14_OFF[11:6] GEN3_FCOEF_LANE14_POST_CURSOR - GEN3_FCOEF_LANE15_14_OFF[14:12] GEN6_FCOEF_LANE14_PRE_CURSOR_2 - GEN3_FCOEF_LANE15_14_OFF[21:16] GEN3_FCOEF_LANE15_PRE_CURSOR - GEN3_FCOEF_LANE15_14_OFF[27:22] GEN3_FCOEF_LANE15_POST_CURSOR - GEN3_FCOEF_LANE15_14_OFF[30:28] GEN6_FCOEF_LANE15_PRE_CURSOR_2 - GEN3_EQ_CONTROL_OFF[3:0] GEN3_EQ_FB_MODE - GEN3_EQ_CONTROL_OFF[4] GEN3_EQ_PHASE23_EXIT_MODE - GEN3_EQ_CONTROL_OFF[5] GEN3_EQ_EVAL_2MS_DISABLE - GEN3_EQ_CONTROL_OFF[7] GEN3_EQ_EVAL_2MS_EXTEND - GEN3_EQ_CONTROL_OFF[23:8] GEN3_EQ_PSET_REQ_VEC - GEN3_EQ_CONTROL_OFF[24] GEN3_EQ_FOM_INC_INITIAL_EVAL - GEN3_EQ_CONTROL_OFF[25] GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[4:0] GEN3_EQ_FMDC_T_MIN_PHASE23 - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[9:5] GEN3_EQ_FMDC_N_EVALS - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[13:10] GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[17:14] GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[21:18] GEN6_EQ_FMDC_MAX_PRE_CURSOR2_DELTA Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| GEN3 |
0x0 |
Gen3 Data Rate is selected for shadow register. |
| GEN4 |
0x1 |
Gen4 Data Rate is selected for shadow register. |
| GEN5 |
0x2 |
Gen5 Data Rate is selected for shadow register. |
| GEN6 |
0x3 |
Gen6 Data Rate is selected for shadow register. |
|
[23:23] RW |
GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE
Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[22:22] RW/V |
USP_SEND_8GT_EQ_TS2_DISABLE
Upstream Port Send 8GT/s or 16GT/s EQ TS2 Disable. The base spec defines that USP can optionally send 8GT or 16GT EQ TS2, which implies that USP can set DSP TxPreset value in Gen4 or Gen5 Data Rate. This applies to upstream ports only; It does not apply to downstream ports.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. - If RATE_SHADOW_SEL==00b, this register is RSVD. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate. Value after reset in Gen4/Gen5/Gen6 is DEFAULT_GEN4_USP_SEND_8GT_EQ_TS2_DISABLE/DEFAULT_GEN5_USP_SEND_16GT_EQ_TS2_DISABLE/DEFAULT_GEN6_USP_SEND_16GT_EQ_TS2_DISABLE.
Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
If this register set to 0, USP sends 8GT or 16GT EQ TS2. |
| SET |
0x1 |
If this register set to 1, USP does not send 8GT or 16GT EQ TS2. |
|
[21:21] RW/V |
AUTO_EQ_DISABLE
Autonomous Equalization Disable.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is RSVD. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism. |
| SET |
0x1 |
When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. |
|
[20:19] RO |
RSVDP_19
Reserved for future use.
Reset: hex:0x0;
|
[18:18] RW |
GEN3_DC_BALANCE_DISABLE
DC Balance Disable. Disable DC Balance feature.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[17:17] RW |
GEN3_DLLP_XMT_DELAY_DISABLE
DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
GEN3_EQUALIZATION_DISABLE
Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[15:15] RW |
GEN3_EQ_PSET_COEF_MAP_MODE_PROG
Enable Programmable Table for Gen3 Equalization Presets to Coefficients Mapping, for Gen3, Gen4, Gen5 and Gen6 Data Rate.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shared for Gen3 and Gen4/Gen5/Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[14:14] RO |
RSVDP_14
Reserved for future use.
Reset: hex:0x0;
|
[13:13] RW |
RXEQ_RGRDLESS_RXTS
When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| ASSERT_1US |
0x0 |
mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. |
| ASSERT_500NS |
0x1 |
mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not. |
|
[12:12] RW |
RXEQ_PH01_EN
Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: Note: When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_TX_EQ_NO_RX_EQ |
0x1 |
No Tx equalization |
| TX_EQ_23 |
0x0 |
Tx equalization only in phase 2/3 |
|
[11:11] RW |
EQ_REDO
Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is infinite or you do not want eq requests and redo, setting this bit to 1 will stop the EQ requests and EQ redo so that the link can go ahead to L0 state for packet trasmissions.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[10:10] RW |
EQ_EIEOS_CNT
Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x1 |
Disable |
|
[09:09] RW |
EQ_PHASE_2_3
Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_TX_EQ_RX_EQ_PH01 |
0x0 |
Rx equalization in phase 0/1 |
| TX_EQ_23_RX_EQ_PH01 |
0x1 |
No Rx equalization |
|
[08:08] RW |
DISABLE_SCRAMBLER_GEN_3
Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY).
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x00;
|
[01:01] RW |
NO_SEED_VALUE_CHANGE
If this bit is set to 1, the seed value of LFSR for scrambler at Gen3 rate does not change after LinkUp = 1. This bit takes effect only when CX_AUTO_LANE_FLIP_CTRL_EN is supported. This feature requires both sides of the link support it.
Note: this register is shared for Gen3 and Gen4/Gen5 data rates.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_CHANGE |
0x1 |
Not Change |
|
[00:00] RW |
GEN3_ZRXDC_NONCOMPL
Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rates.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| RCVR_COMPLIES |
0x0 |
The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. |
| RCVR_NOT_COMPLIES |
0x1 |
The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. |
|
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+0x00000894 Register(32 bit) GEN3_EQ_LOCAL_FS_LF_OFF
Gen3 EQ FS and LF Register.
This register holds the Gen3 EQ FS and LF values.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000894 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000fc3 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
| Name |
RSVDP_12 |
GEN3_EQ_LOCAL_FS |
GEN3_EQ_LOCAL_LF |
| Access |
RO |
RW |
RW |
[31:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x00000;
|
[11:06] RW |
GEN3_EQ_LOCAL_FS
Full Swing (FS) Value for Gen3/Gen4 Transmit Equalization. Value Range: 12 through 63 (decimal).
Used when you enable the Programmable Table for Gen3 Equalization Presets to Coefficients Mapping, by writing '1' to the GEN3_EQ_PSET_COEF_MAP_MODE_PROG field of GEN3_RELATED_OFF register. Selects the FS and LF values used by the local PHY. The values are needed in the controller for advertising during Phase1, and for checking during "EQ Master" that the requested coefficients are legal according to rules in section "4.2.3.1 Rules for Transmitter Coefficients" of the PCI Express Base Specification.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x3f;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0c |
Min value |
| MAX_VAL |
0x3f |
Max value |
|
[05:00] RW |
GEN3_EQ_LOCAL_LF
Low Frequency (LF) Value for Gen3/Gen4 Transmit Equalization. Used when you enable the Programmable Table for Gen3 Equalization Presets to Coefficients Mapping, by writing '1' to the GEN3_EQ_PSET_COEF_MAP_MODE_PROG field of GEN3_RELATED_OFF register. Selects the FS and LF values used by the local PHY. The values are needed in the controller for advertising during Phase1, and for checking during "EQ Master" that the requested coefficients are legal according to the rules in section "4.2.3.1 Rules for Transmitter Coefficients" of the PCI Express Base Specification.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x03;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x3f |
Max value |
|
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+0x00000898 Union(32 bit) GEN3_EQ_PSET_COEF_MAP__0
Gen3 EQ Presets to Coefficients Mapping Register.
This register is only used when you enable the Programmable Table for Gen3 Equalization Presets to Coefficients Mapping, by writing '1' to the GEN3_EQ_PSET_COEF_MAP_MODE_PROG field of GEN3_RELATED_OFF register. These registers are programmed through an indirect addressing scheme (using an index register) to reduce the address footprint in the PCI Express extended configuration space. The index register ("Gen3 EQ Preset Index Register") is used to select which Coefficients Mapping Register is being accessed. Therefore, only four bytes of the PCIe extended configuration space address map is used to contain 44 bytes of information. You must write to the index register ("Gen3 EQ Preset Index Register") before you write to this mapping register.
The controller does not automatically update the coefficients table when the "Gen3 EQ FS and LF Register" is updated with new values. Your application must re-program the controller with new coefficient values every time it updates FS and LF. Your application must ensure that the programmed coefficient values satisfy the "Rules for Transmitter Coefficients" defined in Section 4.2.3.1 of the PCI Express Base Specification. The controller does not apply the programmed coefficient values to mac_phy_txdeemph if they do not meet those rules.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000898 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Registerview GEN3_EQ_PSET_COEF_MAP__0-Default
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_1
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_10
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_2
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_3
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_4
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_5
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_6
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_7
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_8
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
Registerview GEN3_EQ_PSET_COEF_MAP__0-GEN3_EQ_PSET_COEF_MAP__0_9
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00010bc0 |
|
|
Unaffected |
0x001c0000 |
|
|
Undefined |
0x001c0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
- |
- |
- |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_21 |
- |
GEN3_EQ_POST_CURSOR_PSET |
GEN3_EQ_CURSOR_PSET |
GEN3_EQ_PRE_CURSOR_PSET |
| Access |
RO |
- |
RW |
RW |
RW |
[31:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x000;
|
[17:12] RW |
GEN3_EQ_POST_CURSOR_PSET
Post-cursor (C+1) Coefficient. The default (DEFAULT_GEN3_EQ_POSTCURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 5 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
|
[11:06] RW |
GEN3_EQ_CURSOR_PSET
Cursor (C0) Coefficient. Note: Default is DEFAULT_GEN3_EQ_LOCAL_FS -DEFAULT_GEN3_EQ_PRECURSOR_PSETi -DEFAULT_GEN3_EQ_POSTCURSOR_PSETi that is, C0 =FS - abs(C-1) - abs(C+1)
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x2f;
|
[05:00] RW |
GEN3_EQ_PRE_CURSOR_PSET
Pre-cursor (C-1) Coefficient. The default (DEFAULT_GEN3_EQ_PRECURSOR_PSETi) is defined in the table in the "Programming Registers" section of the "Gen3 Equalization Details and Example" appendix in the Databook.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate, lower 4 bits only are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x0000089c Register(32 bit) GEN3_EQ_PSET_INDEX_OFF
Gen3 EQ Preset Index Register.
The preset registers are programmed through an indirect addressing scheme (using this index register) to reduce the address footprint in the PCI Express extended configuration space. The size of the required port logic space does not depend on the number of regions defined as the index register is used to select which preset is being accessed.
Viewportdepth: 11
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100089c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_4 |
GEN3_EQ_PSET_INDEX |
| Access |
RO |
RW |
[31:04] RO |
RSVDP_4
Reserved for future use.
Reset: hex:0x0000000;
|
[03:00] RW |
GEN3_EQ_PSET_INDEX
Preset index i, where i =0, 1,2,..,10. This is the index used for accessing (using register indirect addressing mode) the "Gen3 EQ Presets to Coefficients Mapping Registers". This register is only used when you enable the Programmable Table for Gen3 Equalization Presets to Coefficients Mapping, by writing '1' to the GEN3_EQ_PSET_COEF_MAP_MODE_PROG field of GEN3_RELATED_OFF register.
Note: When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shared for Gen3 and Gen4/Gen5/Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
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+0x000008a4 Register(32 bit) GEN3_EQ_COEFF_LEGALITY_STATUS_OFF
Gen3 EQ Status Register.
This register is only used when you enable the Programmable Table for Gen3 Equalization Presets to Coefficients Mapping, by writing '1' to the GEN3_EQ_PSET_COEF_MAP_MODE_PROG field of GEN3_RELATED_OFF register. This is used to validate the FS, LF, and Coefficient values that your application has programmed. Your application should always validate the programmed values.
It is set by the controller when you program it with illegal coefficients. For more information on legal coefficient values, see Section "4.2.3.1. Rules for Transmitter Coefficients" of the PCI Express Base Specification.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008a4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000000 |
|
|
Unaffected |
0x00000001 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_1 |
GEN3_EQ_VIOLATE_COEF_RULES |
| Access |
RO |
RO/V |
[31:01] RO |
RSVDP_1
Reserved for future use.
Reset: hex:0x00000000;
|
[00:00] RO/V |
GEN3_EQ_VIOLATE_COEF_RULES
Programmable Coefficients Legality Status. This bit is only valid after programming a coefficient into the mapping table. This bit is set if the most recently programmed coefficient ("Gen3 EQ Presets to Coefficients Mapping Registers" violate any of the following rules: Rules for Gen3/4/5 speed - abs(C-1) <= (FS/4) - abs(C-1) + C0 + abs(C+1) =FS - abs(C0) - abs(C-1) - abs(C+1) >= LF Rules for Gen6 speed - abs(C-1) <= (FS/4) - abs(C-2) + abs(C-1) + C0 + abs(C+1) =FS - abs(C0) + abs(C-2) - abs(C-1) - abs(C+1) >= LF - abs(C-2) <= (FS/8) Your application should always check the status after it programs each coefficient, so that it then knows which preset number had the illegal coefficients.
Note: You should ignore the value in this field until you have written/updated the programmable coefficients. Although the value of this register field is '0' during reset, it gets set to '1' almost immediately after the reset is removed. This is because the current coefficient defaults to '0', which is always illegal. So if this field is read before you program the coefficient mapping table, then it is '1'.
This bit is automatically cleared when you read it.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
Clear |
| SET |
0x1 |
Set |
|
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+0x000008a8 Register(32 bit) GEN3_EQ_CONTROL_OFF
Gen3 EQ Control Register.
This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008a8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0d07ff61 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
| Name |
RSVDP_31 |
GEN3_SUPPORT_FINITE_EQ_REQUEST |
GEN3_EQ_REQ_NUM |
GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP |
GEN3_EQ_PSET_REQ_AS_COEF |
GEN3_EQ_FOM_INC_INITIAL_EVAL |
GEN3_EQ_PSET_REQ_VEC |
GEN3_EQ_EVAL_2MS_EXTEND |
GEN3_LOWER_RATE_EQ_REDO_ENABLE |
GEN3_EQ_EVAL_2MS_DISABLE |
GEN3_EQ_PHASE23_EXIT_MODE |
GEN3_EQ_FB_MODE |
| Access |
RO |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
RW/V |
[31:31] RO |
RSVDP_31
Reserved for future use.
Reset: hex:0x0;
|
[30:30] RW/V |
GEN3_SUPPORT_FINITE_EQ_REQUEST
Support finite EQ requests for USP. Note: Gen3, Gen4 and Gen5 share the same register bit and have the same feature.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SUPPORT |
0x1 |
Support |
| UNSUPPORT |
0x0 |
Do not support |
|
[29:27] RW/V |
GEN3_EQ_REQ_NUM
The number of back-to-back equalization redo requests at a given Gen3, Gen4 and Gen5 data rate for USP. After counting the EQ redo requests which are equal to or larger than the number set, the USP stops any EQ redo requests at the data rate. If changing speed, the USP controller clears the counter to 0. Then re-start to count the requests after changing speed back to the data rate for the USP. Note: Gen3, Gen4 and Gen5 share the same register bits and have the same feature.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x7 |
Max value |
| MIN_VAL |
0x0 |
Min value |
|
[26:26] RW/V |
GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP
Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. Note: Gen3 and Gen4 share the same register bit and have the same feature.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DO_NOT_REQ |
0x0 |
Do not request |
| REQ |
0x1 |
Request |
|
[25:25] RW/V |
GEN3_EQ_PSET_REQ_AS_COEF
GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0;
|
[24:24] RW/V |
GEN3_EQ_FOM_INC_INITIAL_EVAL
Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate. Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DO_NOT_INCLUDE |
0x0 |
Do not include |
| INCLUDE |
0x1 |
Include |
|
[23:08] RW/V |
GEN3_EQ_PSET_REQ_VEC
Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows:
Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase.
Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0x0000000000000000: No preset be requested and evaluated in EQ Master Phase - 0x000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 0x000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 0x000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 0x000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 0x000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 0x000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 0x000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 0x000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 0x000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 0x00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 0x000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: Reserved Note: You must contact your PHY vendor to ensure 24 ms timeout does not occur in presets requests in EQ master phase, that is, you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout. Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x07ff;
| Valid Values |
| Name | Value(s) | Description |
| Max_field_value |
0x0ffff |
Max value |
| Min_field_value |
0x0 |
Zero value |
|
[07:07] RW/V |
GEN3_EQ_EVAL_2MS_EXTEND
Phase2_3 extend default Timeout from 2 ms to 4 ms. In Phase2 for USP (Phase3 if DSP) when PHY require more response time to the assertion of RxEqEval timeout is extended to 4 ms Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _2MS |
0x0 |
Use default 2ms timeout |
| _4MS |
0x1 |
Extend timeout of PHY response to 4ms. |
|
[06:06] RW/V |
GEN3_LOWER_RATE_EQ_REDO_ENABLE
Support EQ redo and lower rate change. To access this field, RATE_SHADOW_SEL should be set to 0. Note: Gen3 and Gen4 share the same register bit and have the same feature.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUP |
0x0 |
Not supported |
| SUP |
0x1 |
Supported |
|
[05:05] RW/V |
GEN3_EQ_EVAL_2MS_DISABLE
Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval. Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| ABORT_CURRENT_EVA |
0x0 |
Abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout |
| IGNORE_2MS_TIMEOUT |
0x1 |
Ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval. |
|
[04:04] RW/V |
GEN3_EQ_PHASE23_EXIT_MODE
Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2" For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2" Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure Of Merit mode complete before 24ms timeout. For more information, see GEN3_EQ_PSET_REQ_VEC Register.
Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| RCVRY_EQ |
0x1 |
USP: Recovery.Equalization.Phase3; DSP: Recovery.Equalization.RcvrLock |
| RCVRY_SPEED |
0x0 |
Recovery.Speed |
|
[03:00] RW/V |
GEN3_EQ_FB_MODE
Feedback Mode. Other values are reserved. Note: - When CX_GEN4_SPEED/CX_GEN5_SPEED/CX_GEN6_SPEED, this register is shadow register for Gen3 and Gen4/Gen5/Gen6 data rate. - If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. - If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. - If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. - If RATE_SHADOW_SEL==11b, this register is for Gen6 data rate. Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DIR_CHG |
0x0 |
Direction Change |
| FOM |
0x1 |
Figure Of Merit |
|
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+0x000008b4 Register(32 bit) ORDER_RULE_CTRL_OFF
Order Rule Control Register.
When CC_ORDRB_EN is set to '1', it affects only the RADM ordering and not the AXI bridge or Order Buffering.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008b4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_16 |
CPL_PASS_P |
NP_PASS_P |
| Access |
RO |
RW |
RW |
[31:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0000;
|
[15:08] RW |
CPL_PASS_P
Completion Passing Posted Ordering Rule Control.
Determines if CPL can pass halted P queue.
TDISP Prot :WP
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| CPL_CAN_NOT_PASS |
0x0 |
CPL can not pass P (recommended) |
| CPL_CAN_PASS |
0x1 |
CPL can pass P |
|
[07:00] RW |
NP_PASS_P
Non-Posted Passing Posted Ordering Rule Control.
Determines if NP can pass halted P queue.
TDISP Prot :WP
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| NP_CAN_NOT_PASS |
0x0 |
NP can not pass P (recommended). |
| NP_CAN_PASS |
0x1 |
NP can pass P |
|
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+0x000008b8 Register(32 bit) PIPE_LOOPBACK_CONTROL_OFF
PIPE Loopback Control Register.
This register controls the PIPE Loopback.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008b8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully defined |
0x00000003 |
|
|
Unaffected |
0x07000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
| Name |
PIPE_LOOPBACK |
RSVDP_27 |
RXSTATUS_VALUE |
RSVDP_22 |
RXSTATUS_LANE |
LPBK_RXVALID |
| Access |
RW |
RO |
WS/V |
RO |
RW |
RW |
[31:31] RW |
PIPE_LOOPBACK
PIPE Loopback Enable.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[30:27] RO |
RSVDP_27
Reserved for future use.
Reset: hex:0x0;
|
[26:24] WS/V |
RXSTATUS_VALUE
RXSTATUS_VALUE is an internally reserved field. Do not use.
Reset: hex:0x0;
|
[23:22] RO |
RSVDP_22
Reserved for future use.
Reset: hex:0x0;
|
[21:16] RW |
RXSTATUS_LANE
RXSTATUS_LANE is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x00;
|
[15:00] RW |
LPBK_RXVALID
LPBK_RXVALID is an internally reserved field. Do not use.
Note: This register field is sticky.
Reset: hex:0x0003;
|
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+0x000008bc Register(32 bit) MISC_CONTROL_1_OFF
DBI Read-Only Write Enable Register.
This is the DBI Read-Only write enable register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008bc at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x02474048 |
|
|
Unaffected |
0x3c800010 |
|
|
Undefined |
0x3c800010 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
- |
- |
- |
- |
1 |
0 |
- |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
- |
1 |
0 |
0 |
0 |
| Name |
RSVDP_30 |
- |
ERR_INJ_WR_DISABLE |
RASDES_REG_PF0_ONLY |
- |
PORT_LOGIC_WR_DISABLE |
P2P_ERR_RPT_CTRL |
P2P_TRACK_CPL_TO_REG |
TARGET_ABOVE_CONFIG_LIMIT_REG |
CONFIG_LIMIT_REG |
CFG_TLP_BYPASS_EN_REG |
CPLQ_MNG_EN |
ARI_DEVICE_NUMBER |
- |
SIMPLIFIED_REPLAY_TIMER |
UR_CA_MASK_4_TRGT1 |
DEFAULT_TARGET |
DBI_RO_WR_EN |
| Access |
RO |
- |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW/V |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW/V |
[31:30] RO |
RSVDP_30
Reserved for future use.
Reset: hex:0x0;
|
[25:25] RW |
ERR_INJ_WR_DISABLE
Disable Error Injection enable bits write from wire side.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
|
[24:24] RW |
RASDES_REG_PF0_ONLY
Allows only Physical Function 0 (PF0) to access the RAS DES Extended Capability registers.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[22:22] RW |
PORT_LOGIC_WR_DISABLE
Disable port logic register write from wire side.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
|
[21:21] RW |
P2P_ERR_RPT_CTRL
Determines whether to enable Peer to Peer (P2P) error reporting.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable P2P error reporting |
| ENABLE |
0x1 |
Enable P2P error reporting |
|
[20:20] RW |
P2P_TRACK_CPL_TO_REG
Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DO_NOT_TRACk |
0x0 |
Do not track completion |
| TRACK |
0x1 |
Track completion |
|
[19:18] RW |
TARGET_ABOVE_CONFIG_LIMIT_REG
Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values:
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| ELBI |
0x1 |
ELBI |
| TRGT1 |
0x2 |
TRGT1 |
|
[17:08] RW/V |
CONFIG_LIMIT_REG
Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of TARGET_ABOVE_CONFIG_LIMIT_REG field. Your application must set a proper value for this field based on your extended configuration registers. For more information, see the "CDM/ELBI Register Space Access Through CFG Request" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x340;
|
[07:07] RW |
CFG_TLP_BYPASS_EN_REG
Setting of this field defines how to decide the destination of Configuration requests. Note: When app_req_retry_en is asserted, the setting of this field is ignored.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG, regardless the value of CONFIG_LIMIT_REG. |
| ZERO |
0x0 |
Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG, depending on the setting of CONFIG_LIMIT_REG. Refer to the definition of CONFIG_LIMIT_REG for details. |
|
[06:06] RW |
CPLQ_MNG_EN
This field enables the Completion Queue Management feature.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[05:05] RW |
ARI_DEVICE_NUMBER
When ARI is enabled, this field enables use of the device ID.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[03:03] RW |
SIMPLIFIED_REPLAY_TIMER
Enables Simplified Replay Timer (Gen4). For more information, see "Transmit Replay" in "Transmit TLP Processing" section in the "Controller Operations" chapter of the Databook. Simplified Replay Timer can have the following Values: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b. The Simplified Replay Timer value must not be changed while the link is in use.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[02:02] RW |
UR_CA_MASK_4_TRGT1
When this field is set to '1', the controller suppresses error logging, error message generation, and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is, when DEFAULT_TARGET =1). For more information, see "Advanced Error Handling For Received TLPs" chapter of the Databook.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
Clear |
| SET |
0x1 |
Set |
|
[01:01] RW |
DEFAULT_TARGET
Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. For more information, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing" section of the "Controller Operations" chapter of the Databook.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DROP_IO_MEM_REQ |
0x0 |
The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status is generated for non-posted requests. |
| FWD_IO_MEM_UR_CA_CRS |
0x1 |
The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application. |
|
[00:00] RW/V |
DBI_RO_WR_EN
Write to RO Registers Using DBI. For more information, see "Writing to Read-Only Registers" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. |
| CLEAR |
0x0 |
Clear |
|
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+0x000008c0 Register(32 bit) MULTI_LANE_CONTROL_OFF
UpConfigure Multi-lane Control Register.
Used when upsizing or downsizing the link width through Configuration state without bringing the link down.
For more information, see the "Link Establishment" section in the "Controller
Operations" chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008c0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_9 |
RELIABILITY_LINK_WIDTH_CHANGE_ENABLE |
UPCONFIGURE_SUPPORT |
DIRECT_LINK_WIDTH_CHANGE |
TARGET_LINK_WIDTH |
| Access |
RO |
RW |
RW |
RW/V |
RW |
[31:09] RO |
RSVDP_9
Reserved for future use.
Reset: hex:0x000000;
|
[08:08] RW |
RELIABILITY_LINK_WIDTH_CHANGE_ENABLE
Reduce link width for reliability reasons. RELIABILITY_LINK_WIDTH_CHANGE_ENABLE permits reducing link width for reliability reasons through DIRECT_LINK_WIDTH_CHANGE/TARGET_LINK_WIDTH, irrespective of PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG and UPCONFIGURE_SUPPORT.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
The controller follows behaviour described under DIRECT_LINK_WIDTH_CHANGE, irrespective of PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG and UPCONFIGURE_SUPPORT. |
| CLEAR |
0x0 |
Clear |
|
[07:07] RW |
UPCONFIGURE_SUPPORT
Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[06:06] RW/V |
DIRECT_LINK_WIDTH_CHANGE
Directed Link Width Change. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure or autonomous width downsizing in the Configuration state. The controller self-clears this field when the controller accepts this request.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
The controller always moves to Configuration state through Recovery state when this bit is set to '1'. |
| CLEAR |
0x0 |
Clear |
|
[05:00] RW |
TARGET_LINK_WIDTH
Target Link Width.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W TDISP Prot :WDB
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| NOT_START |
0x0 |
Controller does not start upconfigure or autonomous width downsizing in the Configuration state. |
| X1 |
0x1 |
x1 |
| X16 |
0x10 |
x16 |
| X2 |
0x2 |
x2 |
| X4 |
0x4 |
x4 |
| X8 |
0x08 |
x8 |
| X32 |
0x20 |
x32 |
|
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+0x000008c4 Register(32 bit) PHY_INTEROP_CTRL_OFF
PHY Interoperability Control Register.
This register controls controller PHY dependent behavior.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008c4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x40064a7f |
|
|
Unaffected |
0x80000100 |
|
|
Undefined |
0x80000100 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
- |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
- |
PHY_PERST_ON_WARM_RESET |
PHY_RST_TIMER |
P2NOBEACON_ENABLE |
L1_CLK_SEL |
L1_NOWAIT_P1 |
- |
RSVDP_7 |
RXSTANDBY_CONTROL |
| Access |
- |
RW |
RW |
RW |
RW |
RO |
- |
RO |
RW |
[30:30] RW |
PHY_PERST_ON_WARM_RESET
Control whether the Power Management Controller will drive pm_req_phy_perst during a Warm Reset (PERST# assertion without cycling of power).
Note: This register field is sticky.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
DO NOT Drive pm_req_phy_perst during a Warm Reset. |
| ENABLE |
0x1 |
Drive pm_req_phy_perst during a Warm Reset. |
|
[29:12] RW |
PHY_RST_TIMER
Control the duration of the PHY reset (PIPE and PMA). Duration is in aux clock cycles (0 to 262,142).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00064;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x3ffff |
Max value. |
| MIN_VAL |
0x0 |
Zero value. |
|
[11:11] RW |
P2NOBEACON_ENABLE
P2.NoBeacon Enable bit. Note:This field is reserved (fixed to '0') if CX_P2NOBEACON_ENABLE is not set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| ENCODING |
0x0 |
Controller drives P2 encoding for PHY power down state, when the link goes to L2. |
| NO_BEACON_ENCODING |
0x1 |
Controller drives P2. NoBeacon encoding for PHY power down state, when the link goes to L2. |
|
[10:10] RW |
L1_CLK_SEL
L1 Clock control bit.
This field is reserved for internal use.
You should not write to this field and change the default unless specifically instructed by Synopsys support.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CAN_REQ |
0x0 |
Controller requests aux_clk switch and core_clk gating in L1. |
| NO_REQ |
0x1 |
Controller does not request aux_clk switch and core_clk gating in L1. |
|
[09:09] RO |
L1_NOWAIT_P1
L1 entry control bit.
This field is reserved for internal use.
You should not write to this field and change the default unless specifically instructed by Synopsys support.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| NO_WAIT_FOR_ACK |
0x1 |
Controller does not wait for PHY to acknowledge transition to P1 before entering L1. |
| WAIT_FOR_ACK |
0x0 |
Controller waits for the PHY to acknowledge transition to P1 before entering L1. |
|
[07:07] RO |
RSVDP_7
Reserved for future use.
Reset: hex:0x0;
|
[06:00] RW |
RXSTANDBY_CONTROL
Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake.
This field is reserved for internal use.
You should not write to this field and change the default unless specifically instructed by Synopsys support. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus Handshake
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x7f;
| Valid Values |
| Name | Value(s) | Description |
| Max_bits_value |
0x7f |
Max value |
| Min_bits_value |
0x0 |
Zero value |
|
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+0x000008c8 Register(32 bit) TRGT_CPL_LUT_DELETE_ENTRY_OFF
TRGT_CPL_LUT Delete Entry Control register.
Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason.
Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI manager read channel) corresponding to previously received non-posted requests from the PCIe wire.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008c8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DELETE_EN |
LOOK_UP_ID |
| Access |
WS/V |
RW |
[31:31] WS/V |
DELETE_EN
This is a one-shot bit. This is a self-clearing register field. Reading from this register field always returns a '0'.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. |
| CLEAR |
0x0 |
Clear |
|
[30:00] RW |
LOOK_UP_ID
This number selects one entry to delete of the TRGT_CPL_LUT.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x000008cc Register(32 bit) LINK_FLUSH_CONTROL_OFF
Link Reset Request Flush Control Register.
This register controls link reset request flush behaviour.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008cc at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0xff000001 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
| Name |
AUTO_FLUSH_TIMEOUT |
RSVDP_1 |
AUTO_FLUSH_EN |
| Access |
RW |
RO |
RW |
[31:24] RW |
AUTO_FLUSH_TIMEOUT
Timeout Value (ms) for automatic flushing. The timer acts as a watch dog timer during the auto flushing. The timer counts when there are pending outbound requests and the PCIe TX link is not transmitting any of these requests. The timer is clocked by core_clk.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0xff;
|
[23:01] RO |
RSVDP_1
Reserved for future use.
Reset: hex:0x000000;
|
[00:00] RW |
AUTO_FLUSH_EN
Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the application. The flushing process is initiated if any of the following events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset. If you disable automatic flushing, your application is responsible for resetting the PCIe controller, including the AXI Bridge (when present). For more information see "Warm and Hot Resets" section in the Architecture chapter of the Databook.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
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+0x000008d0 Register(32 bit) AMBA_ERROR_RESPONSE_DEFAULT_OFF
AXI Bridge Subordinate Error Response Register.
This register holds the AXI bridge subordinate error responses.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008d0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00009c00 |
|
|
Unaffected |
0xcfff0000 |
|
|
Undefined |
0xcfff0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
RSVDP_28 |
- |
AMBA_ERROR_RESPONSE_MAP |
RSVDP_5 |
AMBA_ERROR_RESPONSE_CRS |
AMBA_ERROR_RESPONSE_VENDORID |
RSVDP_1 |
AMBA_ERROR_RESPONSE_GLOBAL |
| Access |
- |
RO |
- |
RW |
RO |
RW |
RW |
RO |
RW |
[29:28] RO |
RSVDP_28
Reserved for future use.
Reset: hex:0x0;
|
[15:10] RW |
AMBA_ERROR_RESPONSE_MAP
AXI Subordinate Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI subordinate responses, slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - 0 -- 0x0: UR (unsupported request) -> DECERR -- 0x1: UR (unsupported request) -> SLVERR - 1 -- 0x0: CRS (configuration retry status) -> DECERR -- 0x1: CRS (configuration retry status) -> SLVERR - 2 -- 0x0: CA (completer abort) -> DECERR -- 0x1: CA (completer abort) -> SLVERR - 3: RESERVED (0x0) - 4: RESERVED (0x0) - 5 -- 0x0: Completion Timeout -> DECERR -- 0x1: Completion Timeout -> SLVERR. The AXI bridge internally drops (processes internally but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave interface. The controller sets the AXI subordinate read databus to 0xFFFF for all error responses.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x27;
| Valid Values |
| Name | Value(s) | Description |
| Max_value |
0x3f |
Max value |
| Min_value |
0x0 |
Zero value |
|
[09:05] RO |
RSVDP_5
Reserved for future use.
Reset: hex:0x00;
|
[04:03] RW |
AMBA_ERROR_RESPONSE_CRS
CRS Slave Error Response Mapping. Determines the AXI subordinate response for CRS completions. For more information see "Error Handling" in the AXI chapter of the Databook.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| OK_ |
0x0 |
OKAY |
| OK_CRS_CMPL |
0x1 |
OKAY with all FFFF_FFFF data for all CRS completions |
| OK_READ_REQ |
0x2 |
OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions |
| SLVERR_DECERR |
0x3 |
SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Subordinate error response mapping) |
|
[02:02] RW |
AMBA_ERROR_RESPONSE_VENDORID
Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI subordinate response for errors on reads to non-existent Vendor ID register. For more information see "Error Handling" in the AXI chapter of the Databook.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _ERR_ |
0x1 |
SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Subordinate error response mapping) |
| _OK_ |
0x0 |
OKAY (with FFFF data). |
|
[01:01] RO |
RSVDP_1
Reserved for future use.
Reset: hex:0x0;
|
[00:00] RW |
AMBA_ERROR_RESPONSE_GLOBAL
Global Slave Error Response Mapping. Determines the AXI subordinate response for all error scenarios on non-posted requests. For more information see "Error Handling" in the AXI chapter of the Databook. The error response mapping is not applicable to Non-existent Vendor ID register reads.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ERR_ |
0x1 |
SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Subordinate error response mapping) |
| OK_ |
0x0 |
OKAY (with FFFF data for non-posted requests) |
|
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+0x000008d4 Register(32 bit) AMBA_LINK_TIMEOUT_OFF
Link Down AXI Bridge Subordinate Timeout Register.
If your application AXI manager issues outbound requests to the AXI bridge subordinate interface before the PCIe link is operational, the controller starts a "flush" timer. The timeout value of the timer is set by this register. If the timer times out before the PCIe link is operational, the bridge TX request queues are flushed. For more information, see the "AXI Bridge Initialization, Clocking and Reset" section in the AXI chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008d4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000032 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
| Name |
RSVDP_9 |
LINK_TIMEOUT_ENABLE_DEFAULT |
LINK_TIMEOUT_PERIOD_DEFAULT |
| Access |
RO |
RW |
RW |
[31:09] RO |
RSVDP_9
Reserved for future use.
Reset: hex:0x000000;
|
[08:08] RW |
LINK_TIMEOUT_ENABLE_DEFAULT
Disable Flush.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x1 |
You can disable the flush feature by setting this field to '1'. |
| ENABLE |
0x0 |
Enable |
|
[07:00] RW |
LINK_TIMEOUT_PERIOD_DEFAULT
Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI subordinate interface requests and the PCIe TX link is not transmitting any of these requests. The timer is clocked by core_clk.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x32;
|
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+0x000008d8 Register(32 bit) AMBA_ORDERING_CTRL_OFF
AXI Bridge Ordering Control.
Controls the AXI Bridge Ordering when CC_ORDRB_EN is not set.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008d8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_8 |
AX_MSTR_ZEROLREAD_FW |
RSVDP_5 |
AX_MSTR_ORDR_P_EVENT_SEL |
RSVDP_2 |
AX_SNP_EN |
RSVDP_0 |
| Access |
RO |
RW |
RO |
RW/V |
RO |
RW |
RO |
[31:08] RO |
RSVDP_8
Reserved for future use.
Reset: hex:0x000000;
|
[07:07] RW |
AX_MSTR_ZEROLREAD_FW
AXI Manager Zero Length Read Forward to the application.
The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read, implementing the PCIe express flush semantics of the Posted transactions.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| _0_LN_RD_FWD |
0x1 |
The zero length Read is forward to the application. |
| _0_LN_RD_TERMINATE |
0x0 |
The zero length Read is terminated at the DW PCIe AXI bridge manager |
|
[06:05] RO |
RSVDP_5
Reserved for future use.
Reset: hex:0x0;
|
[04:03] RW/V |
AX_MSTR_ORDR_P_EVENT_SEL
AXI Manager Posted Ordering Event Selector.
This field selects how the manager interface determines when a P write is completed when enforcing the PCIe ordering rule, "NP must not pass P" at the AXI Manager Interface. The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same address. Therefore, the bridge manager does not issue any NP requests until all outstanding P writes reach their destination. It does this by waiting for the all of the write responses on the B channel. This can affect the performance of the manager read channel. For scenarios where the interconnect serializes the AXI manager "AW", "W" and "AR" channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave.
Note: This setting will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP write transactions which are always serialized with P write transactions. Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| AW |
0x1 |
AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. |
| B |
0x0 |
B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave (default). |
| W |
0x2 |
W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. |
| RSVD |
0x3 |
Reserved |
|
[02:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x0;
|
[01:01] RW |
AX_SNP_EN
AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner. For more information, see the "Optional Serialization of AXI Subordinate Non-posted Requests" section in the AXI chapter of the Databook.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[00:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x0;
|
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+0x000008e0 Register(32 bit) COHERENCY_CONTROL_1_OFF
Cache Coherency Control Register 1.
This register controls the cache coherency operation.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008e0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CFG_MEMTYPE_BOUNDARY_LOW_ADDR |
RSVDP_1 |
CFG_MEMTYPE_VALUE |
| Access |
RW |
RO |
RW |
[31:02] RW |
CFG_MEMTYPE_BOUNDARY_LOW_ADDR
Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space region; addresses equal or greater than this value are in the upper address space region.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
[01:01] RO |
RSVDP_1
Reserved for future use.
Reset: hex:0x0;
|
[00:00] RW |
CFG_MEMTYPE_VALUE
Sets the memory type for the lower and upper parts of the address space:
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| LOWER_MEM |
0x1 |
lower = Memory type; upper = Peripheral |
| LOWER_PREPH |
0x0 |
lower = Peripheral; upper = Memory |
|
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+0x000008e8 Register(32 bit) COHERENCY_CONTROL_3_OFF
Cache Coherency Control Register 3.
This register controls the cache coherency operation.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008e8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x87878787 |
|
|
Undefined |
0x87878787 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
0 |
0 |
0 |
0 |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
- |
| Name |
- |
CFG_MSTR_AWCACHE_VALUE |
- |
CFG_MSTR_ARCACHE_VALUE |
- |
CFG_MSTR_AWCACHE_MODE |
- |
CFG_MSTR_ARCACHE_MODE |
- |
| Access |
- |
RW |
- |
RW |
- |
RW |
- |
RW |
- |
[30:27] RW |
CFG_MSTR_AWCACHE_VALUE
Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'.
Note: Not applicable to message requests; for message requests the value of mstr_awcache is always '0000'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[22:19] RW |
CFG_MSTR_ARCACHE_VALUE
Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
|
[14:11] RW |
CFG_MSTR_AWCACHE_MODE
Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled.
Note: for message requests the value of mstr_awcache is always "0000" regardless of the value of this bit.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET_BY_FIELD |
0x1 |
set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field |
| SET_BY_AXI_MASTER |
0x0 |
set automatically by the AXI manager |
|
[06:03] RW |
CFG_MSTR_ARCACHE_MODE
Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET_BY_FIELD |
0x1 |
set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field |
| SET_BY_AXI_MASTER |
0x0 |
set automatically by the AXI manager |
|
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+0x000008f0 Register(32 bit) AXI_MSTR_MSG_ADDR_LOW_OFF
Lower 32-bits of the Programmable AXI Address.
Lower 20 bits of the programmable AXI address to which Messages coming from wire are mapped. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI manager address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008f0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CFG_AXIMSTR_MSG_ADDR_LOW |
CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED |
| Access |
RW |
RO |
[31:12] RW |
CFG_AXIMSTR_MSG_ADDR_LOW
Lower 20-bits of the programmable AXI address for Messages.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000;
|
[11:00] RO |
CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED
Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x000;
|
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+0x000008f4 Register(32 bit) AXI_MSTR_MSG_ADDR_HIGH_OFF
Upper 32-bits of the Programmable AXI Address.
Upper 32 bits of the programmable AXI address to which Messages coming from wire are mapped.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008f4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
CFG_AXIMSTR_MSG_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
CFG_AXIMSTR_MSG_ADDR_HIGH
Upper 32 bits of the programmable AXI address for Messages.
Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x00000000;
|
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+0x000008f8 Register(32 bit) PCIE_VERSION_NUMBER_OFF
PCIe Controller IIP Release Version Number.
The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret.
Using 4.70a (GA) as an example:
- VERSION_NUMBER = 0x3437302a which translates to 470*
- VERSION_TYPE = 0x67612a2a which translates to ga**
Using 4.70a-ea01 as an example:
- VERSION_NUMBER = 0x3437302a which translates to 470*
- VERSION_TYPE = 0x65613031 which translates to ea01
GA is a general release available on www.designware.com
EA is an early release available on a per-customer basis.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008f8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x3631322a |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
| Name |
VERSION_NUMBER |
| Access |
RO |
[31:00] RO |
VERSION_NUMBER
Version Number.
Reset: hex:0x3631322a;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffffffff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
|
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+0x000008fc Register(32 bit) PCIE_VERSION_TYPE_OFF
PCIe Controller IIP Release Version Type.
The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret.
Using 4.70a (GA) as an example:
- VERSION_NUMBER = 0x3437302a which translates to 470*
- VERSION_TYPE = 0x67612a2a which translates to ga**
Using 4.70a-ea01 as an example:
- VERSION_NUMBER = 0x3437302a which translates to 470*
- VERSION_TYPE = 0x65613031 which translates to ea01
GA is a general release available on www.designware.com
EA is an early release available on a per-customer basis.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x010008fc at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x6c633031 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
| Name |
VERSION_TYPE |
| Access |
RO |
[31:00] RO |
VERSION_TYPE
Version Type.
Reset: hex:0x6c633031;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffffffff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
|
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+0x00000940 Register(32 bit) MSIX_ADDRESS_MATCH_LOW_OFF
MSI-X Address Match Low Register.
When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more information, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPs
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000940 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSIX_ADDRESS_MATCH_LOW |
MSIX_ADDRESS_MATCH_RESERVED_1 |
MSIX_ADDRESS_MATCH_EN |
| Access |
RW |
RO |
RW |
[31:02] RW |
MSIX_ADDRESS_MATCH_LOW
MSI-X Address Match Low Address.
Note: This register field is sticky.
Reset: hex:0x00000000;
|
[01:01] RO |
MSIX_ADDRESS_MATCH_RESERVED_1
Reserved.
Note: This register field is sticky.
Reset: hex:0x0;
|
[00:00] RW |
MSIX_ADDRESS_MATCH_EN
MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
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+0x00000944 Register(32 bit) MSIX_ADDRESS_MATCH_HIGH_OFF
MSIX Address Match High Register.
MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more information, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPs
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000944 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSIX_ADDRESS_MATCH_HIGH |
| Access |
RW |
[31:00] RW |
MSIX_ADDRESS_MATCH_HIGH
MSI-X Address Match High Address.
Note: This register field is sticky.
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0ffffffff |
Max value |
| MIN_VAL |
0x0 |
Zero value |
|
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+0x00000948 Register(32 bit) MSIX_DOORBELL_OFF
MSI-X Doorbell Register.
When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more information, see the Interrupts section in the "Controller Operations" chapter of the Databook.
- For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF, the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs.
- For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000948 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSIX_DOORBELL_RESERVED_29_31 |
MSIX_DOORBELL_PF |
MSIX_DOORBELL_VF |
MSIX_DOORBELL_VF_ACTIVE |
MSIX_DOORBELL_TC |
MSIX_DOORBELL_RESERVED_11 |
MSIX_DOORBELL_VECTOR |
| Access |
WS |
WS |
WS |
WS |
WS |
WS |
WS |
[31:29] WS |
MSIX_DOORBELL_RESERVED_29_31
Reserved.
Reset: hex:0x0;
|
[28:24] WS |
MSIX_DOORBELL_PF
MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction.
Reset: hex:0x00;
|
[23:16] WS |
MSIX_DOORBELL_VF
MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.
Reset: hex:0x00;
|
[15:15] WS |
MSIX_DOORBELL_VF_ACTIVE
MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction.
Reset: hex:0x0;
|
[14:12] WS |
MSIX_DOORBELL_TC
MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with.
Reset: hex:0x0;
|
[11:11] WS |
MSIX_DOORBELL_RESERVED_11
Reserved.
Reset: hex:0x0;
|
[10:00] WS |
MSIX_DOORBELL_VECTOR
MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.
Reset: hex:0x000;
|
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+0x0000094c Register(32 bit) MSIX_RAM_CTRL_OFF
MSI-X RAM power mode and debug control register.
When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more information, see the Interrupts section in the "Controller Operations" chapter of the Databook.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0100094c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSIX_RAM_CTRL_RESERVED_26_31 |
MSIX_RAM_CTRL_DBG_PBA |
MSIX_RAM_CTRL_DBG_TABLE |
MSIX_RAM_CTRL_RESERVED_17_23 |
MSIX_RAM_CTRL_BYPASS |
MSIX_RAM_CTRL_RESERVED_10_15 |
MSIX_RAM_CTRL_PBA_SD |
MSIX_RAM_CTRL_PBA_DS |
MSIX_RAM_CTRL_RESERVED_2_7 |
MSIX_RAM_CTRL_TABLE_SD |
MSIX_RAM_CTRL_TABLE_DS |
| Access |
RO |
RW |
RW |
RO |
RW |
RO |
RW |
RW |
RO |
RW |
RW |
[31:26] RO |
MSIX_RAM_CTRL_RESERVED_26_31
Reserved.
Note: This register field is sticky.
Reset: hex:0x00;
|
[25:25] RW |
MSIX_RAM_CTRL_DBG_PBA
MSIX PBA RAM Debug Mode. You can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ENABLE |
0x1 |
Enable. Use this bit to activate the debug mode and allow direct read/write access to the PBA. |
| DISABLE |
0x0 |
Disable |
|
[24:24] RW |
MSIX_RAM_CTRL_DBG_TABLE
MSIX Table RAM Debug Mode. You can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ENABLE |
0x1 |
Enable. Use this bit to activate the debug mode and allow direct read/write access to the Table. |
| DISABLE |
0x0 |
Disable |
|
[23:17] RO |
MSIX_RAM_CTRL_RESERVED_17_23
Reserved.
Note: This register field is sticky.
Reset: hex:0x00;
|
[16:16] RW |
MSIX_RAM_CTRL_BYPASS
MSIX RAM Control Bypass. It is up to the application to ensure the RAMs are in the proper power state before trying to access them. Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
The bypass field, when set, disables the internal generation of low power signals for both RAMs. |
| CLEAR |
0x0 |
Clear |
|
[15:10] RO |
MSIX_RAM_CTRL_RESERVED_10_15
Reserved.
Note: This register field is sticky.
Reset: hex:0x00;
|
[09:09] RW |
MSIX_RAM_CTRL_PBA_SD
MSIX PBA RAM Shut Down.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. |
| CLEAR |
0x0 |
Clear |
|
[08:08] RW |
MSIX_RAM_CTRL_PBA_DS
MSIX PBA RAM Deep Sleep.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. |
| CLEAR |
0x0 |
Clear |
|
[07:02] RO |
MSIX_RAM_CTRL_RESERVED_2_7
Reserved.
Note: This register field is sticky.
Reset: hex:0x00;
|
[01:01] RW |
MSIX_RAM_CTRL_TABLE_SD
MSIX Table RAM Shut Down.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. |
| CLEAR |
0x0 |
Clear |
|
[00:00] RW |
MSIX_RAM_CTRL_TABLE_DS
MSIX Table RAM Deep Sleep.
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. |
| CLEAR |
0x0 |
Clear |
|
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+0x00000b10 Register(32 bit) PL_APP_BUS_DEV_NUM_STATUS_OFF
Application driven bus and device number register.
This register reflects the application driven bus and device number.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_16 |
RC_DSW_BUS_NUM |
RC_DSW_DEV_NUM |
RSVDP_0 |
| Access |
RO |
RO |
RO |
RO |
[31:16] RO |
RSVDP_16
Reserved for future use.
Reset: hex:0x0000;
|
[15:08] RO |
RC_DSW_BUS_NUM
This field reflects the value of bus number driven on app_bus_num input signal by your application.
Note: This register field is sticky.
Reset: hex:0x00;
|
[07:03] RO |
RC_DSW_DEV_NUM
This field reflects the value of device number driven on app_device_num input signal by your application.
Note: This register field is sticky.
Reset: hex:0x00;
|
[02:00] RO |
RSVDP_0
Reserved for future use.
Reset: hex:0x0;
|
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+0x00000b1c Register(32 bit) PCIPM_TRAFFIC_CTRL_OFF
TLP Traffic during Non-D0 State Control Register.
This register provides control over TLP Traffic during Non-D0 States.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b1c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_8 |
PCIPM_RESERVED_4_7 |
PCIPM_NEW_TLP_CLIENT2_BLOCKED |
PCIPM_NEW_TLP_CLIENT1_BLOCKED |
PCIPM_NEW_TLP_CLIENT0_BLOCKED |
PCIPM_VDM_TRAFFIC_BLOCKED |
| Access |
RO |
RO |
RW |
RW |
RW |
RW |
[31:08] RO |
RSVDP_8
Reserved for future use.
Reset: hex:0x000000;
|
[07:04] RO |
PCIPM_RESERVED_4_7
Reserved.
Note: This register field is sticky.
Reset: hex:0x0;
|
[03:03] RW |
PCIPM_NEW_TLP_CLIENT2_BLOCKED
This field indicates that all TLPs transmitted by Client 2 interface are blocked during non-D0 states.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[02:02] RW |
PCIPM_NEW_TLP_CLIENT1_BLOCKED
This field indicates that all TLPs transmitted by Client 1 interface are blocked during non-D0 states.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[01:01] RW |
PCIPM_NEW_TLP_CLIENT0_BLOCKED
This field indicates that all TLPs transmitted by Client 0 interface are blocked during non-D0 states.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[00:00] RW |
PCIPM_VDM_TRAFFIC_BLOCKED
This field indicates that VDM Message TLPs are blocked during non-D0 states.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
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+0x00000b40 Register(32 bit) AUX_CLK_FREQ_OFF
Auxiliary Clock Frequency Control Register.
This register controls the auxiliary clock frequency.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b40 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000000a |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
| Name |
RSVDP_10 |
AUX_CLK_FREQ |
| Access |
RO |
RW |
[31:10] RO |
RSVDP_10
Reserved for future use.
Reset: hex:0x000000;
|
[09:00] RW |
AUX_CLK_FREQ
The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted. If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00a;
|
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+0x00000b48 Register(32 bit) POWERDOWN_CTRL_STATUS_OFF
Powerdown Control and Status Register.
This is the Powerdown Control and Status register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b48 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000220 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_12 |
POWERDOWN_PHY_POWERDOWN |
POWERDOWN_MAC_POWERDOWN |
RSVDP_2 |
POWERDOWN_VMAIN_ACK |
POWERDOWN_FORCE |
| Access |
RO |
RO/V |
RO/V |
RO |
RW |
WS/V |
[31:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x00000;
|
[11:08] RO/V |
POWERDOWN_PHY_POWERDOWN
This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller, when the PHY has returned the Phystatus acknowledgment for the Powerdown transition.
Reset: hex:0x2;
|
[07:04] RO/V |
POWERDOWN_MAC_POWERDOWN
This field represents the Powerdown value driven by the controller to the PHY.
Reset: hex:0x2;
|
[03:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x0;
|
[01:01] RW |
POWERDOWN_VMAIN_ACK
Set this bit to 1 if you do not want to perform the handshake with the power-switch after PERST# assertion. By default the controller will perform the handshake with the power-switch if L1 power gating is enabled
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
If you do not want to perform the handshake with the power-switch after PERST# assertion. |
| CLEAR |
0x0 |
Clear |
|
[00:00] WS/V |
POWERDOWN_FORCE
This field is a one shot field. This field could be used for debug purposes in event that the P2 Powerdown transition does not complete. It will allow the controller to proceed with the transition to the P1 Powerdown state. This field always reads back as 1'b0.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| SET |
0x1 |
Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. |
| CLEAR |
0x0 |
Clear |
|
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+0x00000b4c Register(32 bit) PHY_INTEROP_CTRL_2_OFF
PHY Interoperability Control 2 Register.
This register controls controller PHY dependent behavior.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b4c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000010 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_12 |
DSP_PCIPM_L1_ENTER_DELAY |
RSVDP_6 |
PMA_PIPE_RST_DELAY_TIMER |
| Access |
RO |
RW |
RO |
RW |
[31:12] RO |
RSVDP_12
Reserved for future use.
Reset: hex:0x00000;
|
[11:08] RW |
DSP_PCIPM_L1_ENTER_DELAY
For a DSP component, this register field controls the delay between the reception of PM_Enter_L1 DLLP and the start of PCI-PM L1 entry negotiation in aux clock cycles (1 to 15). When using this feature on legacy DMA configurations, the configured value must be greater than three.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x0f |
Max value. |
| MIN_VAL |
0x0 |
Zero value. |
|
[07:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x0;
|
[05:00] RW |
PMA_PIPE_RST_DELAY_TIMER
Control how long the controller should wait to release a PIPE reset (pm_req_phy_rst) after releasing a PMA reset (pm_req_phy_perst). This register should only be used to ensure a correct sequencing of the resets into the PHY. If the application needs to delay the PIPE reset arbitrarily, for example to configure the PHY firmware, Synopsys recommends using the app_hold_phy_rst control signal. There is no need to modify the value of this register when using Synopsys PHYs. Duration is in aux clock cycles.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x10;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VAL |
0x3f |
Max value. |
| MIN_VAL |
0x0a |
Min value. |
|
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+0x00000b80 Register(32 bit) GEN4_LANE_MARGINING_1_OFF
Gen4 Lane Margining 1 Register.
This is the Gen4 Lane Margining 1 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b80 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x05201408 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
| Name |
RSVDP_30 |
GEN4_MARGINING_MAX_VOLTAGE_OFFSET |
RSVDP_23 |
GEN4_MARGINING_NUM_VOLTAGE_STEPS |
RSVDP_14 |
GEN4_MARGINING_MAX_TIMING_OFFSET |
RSVDP_6 |
GEN4_MARGINING_NUM_TIMING_STEPS |
| Access |
RO |
RW |
RO |
RW |
RO |
RW |
RO |
RW |
[31:30] RO |
RSVDP_30
Reserved for future use.
Reset: hex:0x0;
|
[29:24] RW |
GEN4_MARGINING_MAX_VOLTAGE_OFFSET
MMaxVoltageOffset for 16.0 GT/s for Lane Margining at the Receiver.
Offset from default at maximum step value as percentage of one volt. A '0' value might be reported if the vendor chooses not to report the offset when MVoltageSupported is 1b. This value is undefined if MVoltageSupported is 0b.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x05;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x32 |
Max value. |
| MIN_VALUE |
0x5 |
Min value. |
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:16] RW |
GEN4_MARGINING_NUM_VOLTAGE_STEPS
MNumVoltageSteps for 16.0 GT/s for Lane Margining at the Receiver.
Number of voltage steps from default (either up or down), minimum range +/-50mV as measured by the reference equalizer. Voltage offset must increase monotonically. The number of steps in both positive and negative direction from the default sample location must be identical. This value is undefined if MVoltageSupported is 0b.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x20;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x7f |
Max value. |
| MIN_VALUE |
0x20 |
Min value. |
|
[15:14] RO |
RSVDP_14
Reserved for future use.
Reset: hex:0x0;
|
[13:08] RW |
GEN4_MARGINING_MAX_TIMING_OFFSET
MMaxTimingOffset for 16.0 GT/s for Lane Margining at the Receiver.
Offset from default at maximum step value as percentage of a nominal UI. A '0' value might be reported if the vendor chooses not to report the offset.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x14;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x32 |
Max value. |
| MIN_VALUE |
0x14 |
Min value. |
|
[07:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x0;
|
[05:00] RW |
GEN4_MARGINING_NUM_TIMING_STEPS
MNumTimingSteps for 16.0 GT/s for Lane Margining at the Receiver. Number of time steps from default (to either left or right), range must be at least +/-0.2 UI . Timing offset must increase monotonically. The number of steps in both positive (toward the end of the unit interval) and negative (toward the beginning of the unit interval) must be identical.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x08;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x3f |
Max value. |
| MIN_VALUE |
0x6 |
Min value. |
|
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+0x00000b84 Register(32 bit) GEN4_LANE_MARGINING_2_OFF
Gen4 Lane Margining 2 Register.
This is the Gen4 Lane Margining 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b84 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x03011f1f |
|
|
Unaffected |
0x80000000 |
|
|
Undefined |
0x80000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
| Name |
- |
RSVDP_29 |
GEN4_MARGINING_IND_ERROR_SAMPLER |
GEN4_MARGINING_SAMPLE_REPORTING_METHOD |
GEN4_MARGINING_IND_LEFT_RIGHT_TIMING |
GEN4_MARGINING_IND_UP_DOWN_VOLTAGE |
GEN4_MARGINING_VOLTAGE_SUPPORTED |
RSVDP_21 |
GEN4_MARGINING_MAXLANES |
RSVDP_14 |
GEN4_MARGINING_SAMPLE_RATE_TIMING |
RSVDP_6 |
GEN4_MARGINING_SAMPLE_RATE_VOLTAGE |
| Access |
- |
RO |
RW |
RW |
RW |
RW |
RW |
RO |
RW |
RO |
RW |
RO |
RW |
[30:29] RO |
RSVDP_29
Reserved for future use.
Reset: hex:0x0;
|
[28:28] RW |
GEN4_MARGINING_IND_ERROR_SAMPLER
MIndErrorSampler for 16.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Margining does not produce errors (change in the error rate) in data stream (that is, error sampler is independent). |
| MIN_VALUE |
0x0 |
Margining might produce errors in the data stream. |
|
[27:27] RW |
GEN4_MARGINING_SAMPLE_REPORTING_METHOD
MSampleReportingMethod for 16.0 GT/s for Lane Margining at the Receiver.
Indicates whether sampling rates or sample count is supported. One of the two methods is supported by each device.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Indicates sampling rates (MSamplingRateVoltage and MSamplingRateTiming) are supported. |
| MIN_VALUE |
0x0 |
Indicates sample count is supported. |
|
[26:26] RW |
GEN4_MARGINING_IND_LEFT_RIGHT_TIMING
MIndLeftRightTiming for 16.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Indicates independent left/right timing margin is supported. |
| MIN_VALUE |
0x0 |
Indicates independent left/right timing margin is not supported. |
|
[25:25] RW |
GEN4_MARGINING_IND_UP_DOWN_VOLTAGE
MIndUpDownVoltage for 16.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Independent up and down voltage margining is supported. |
| MIN_VALUE |
0x0 |
Independent up and down voltage margining is not supported. |
|
[24:24] RW |
GEN4_MARGINING_VOLTAGE_SUPPORTED
MVoltageSupported for 16.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Voltage margining is supported. |
| MIN_VALUE |
0x0 |
Voltage margining is not supported. |
|
[23:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x0;
|
[20:16] RW |
GEN4_MARGINING_MAXLANES
MMaxLanes for 16.0 GT/s for Lane Margining at the Receiver. Maximum number of Lanes minus 1 that can be margined at the same time. It is recommended that this value be greater than or equal to the number of Lanes in the Link minus 1. Encoding Behavior is undefined if software attempts to margin more than MMaxLanes+1 at the same time.
Note: This value is permitted to exceed the number of Lanes in the Link minus 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x01;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1f |
Max value. |
| MIN_VALUE |
0x0 |
Min value. |
|
[15:14] RO |
RSVDP_14
Reserved for future use.
Reset: hex:0x0;
|
[13:08] RW |
GEN4_MARGINING_SAMPLE_RATE_TIMING
MSamplingRateTiming for 16.0 GT/s for Lane Margining at the Receiver.
Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The MSamplingRateTiming is fixed to 63 internally.
The ratio of bits tested to bits received during timing margining.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1f;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x3f |
Value of 63 is a ratio of 64:64 (all bits received). |
| MIN_VALUE |
0x0 |
Value of 0 is a ratio of 1:64 (1 bit of every 64 bits received). |
|
[07:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x0;
|
[05:00] RW |
GEN4_MARGINING_SAMPLE_RATE_VOLTAGE
MSamplingRateVoltage for 16.0 GT/s for Lane Margining at the Receiver. The ratio of bits tested to bits received during voltage margining.
Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The MSamplingRateVoltage is fixed to 63 internally.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1f;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x3f |
Value of 63 is a ratio of 64:64 (all bits received). |
| MIN_VALUE |
0x0 |
Value of 0 is a ratio of 1:64 (1 bit of every 64 bits received). |
|
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+0x00000b88 Register(32 bit) GEN5_LANE_MARGINING_1_OFF
Gen5 Lane Margining 1 Register.
This is the Gen5 Lane Margining 1 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b88 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x05201408 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
| Name |
RSVDP_30 |
GEN5_MARGINING_MAX_VOLTAGE_OFFSET |
RSVDP_23 |
GEN5_MARGINING_NUM_VOLTAGE_STEPS |
RSVDP_14 |
GEN5_MARGINING_MAX_TIMING_OFFSET |
RSVDP_6 |
GEN5_MARGINING_NUM_TIMING_STEPS |
| Access |
RO |
RW |
RO |
RW |
RO |
RW |
RO |
RW |
[31:30] RO |
RSVDP_30
Reserved for future use.
Reset: hex:0x0;
|
[29:24] RW |
GEN5_MARGINING_MAX_VOLTAGE_OFFSET
MMaxVoltageOffset for 32.0 GT/s for Lane Margining at the Receiver.
Offset from default at maximum step value as percentage of one volt. A '0' value might be reported if the vendor chooses not to report the offset when MVoltageSupported is 1b. This value is undefined if MVoltageSupported is 0b.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x05;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x32 |
Max value. |
| MIN_VALUE |
0x5 |
Min value. |
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:16] RW |
GEN5_MARGINING_NUM_VOLTAGE_STEPS
MNumVoltageSteps for 32.0 GT/s for Lane Margining at the Receiver.
Number of voltage steps from default (either up or down), minimum range +/-50mV as measured by the reference equalizer. Voltage offset must increase monotonically. The number of steps in both positive and negative direction from the default sample location must be identical. This value is undefined if MVoltageSupported is 0b.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x20;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x7f |
Max value. |
| MIN_VALUE |
0x20 |
Min value. |
|
[15:14] RO |
RSVDP_14
Reserved for future use.
Reset: hex:0x0;
|
[13:08] RW |
GEN5_MARGINING_MAX_TIMING_OFFSET
MMaxTimingOffset for 32.0 GT/s for Lane Margining at the Receiver. Offset from default at maximum step value as percentage of a nominal UI. A '0' value might be reported if the vendor chooses not to report the offset.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x14;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x32 |
Max value. |
| MIN_VALUE |
0x14 |
Min value. |
|
[07:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x0;
|
[05:00] RW |
GEN5_MARGINING_NUM_TIMING_STEPS
MNumTimingSteps for 32.0 GT/s for Lane Margining at the Receiver. Number of time steps from default (to either left or right), range must be at least +/-0.2 UI . Timing offset must increase monotonically. The number of steps in both positive (toward the end of the unit interval) and negative (toward the beginning of the unit interval) must be identical.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x08;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x3f |
Max value. |
| MIN_VALUE |
0x6 |
Min value. |
|
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+0x00000b8c Register(32 bit) GEN5_LANE_MARGINING_2_OFF
Gen5 Lane Margining 2 Register.
This is the Gen5 Lane Margining 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b8c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x03011f1f |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
| Name |
RSVDP_29 |
GEN5_MARGINING_IND_ERROR_SAMPLER |
GEN5_MARGINING_SAMPLE_REPORTING_METHOD |
GEN5_MARGINING_IND_LEFT_RIGHT_TIMING |
GEN5_MARGINING_IND_UP_DOWN_VOLTAGE |
GEN5_MARGINING_VOLTAGE_SUPPORTED |
RSVDP_21 |
GEN5_MARGINING_MAXLANES |
RSVDP_14 |
GEN5_MARGINING_SAMPLE_RATE_TIMING |
RSVDP_6 |
GEN5_MARGINING_SAMPLE_RATE_VOLTAGE |
| Access |
RO |
RW |
RW |
RW |
RW |
RW |
RO |
RW |
RO |
RW |
RO |
RW |
[31:29] RO |
RSVDP_29
Reserved for future use.
Reset: hex:0x0;
|
[28:28] RW |
GEN5_MARGINING_IND_ERROR_SAMPLER
MIndErrorSampler for 32.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Margining does not produce errors (change in the error rate) in data stream (that is, error sampler is independent). |
| MIN_VALUE |
0x0 |
Margining might produce errors in the data stream. |
|
[27:27] RW |
GEN5_MARGINING_SAMPLE_REPORTING_METHOD
MSampleReportingMethod for 32.0 GT/s for Lane Margining at the Receiver. Indicates whether sampling rates or sample count is supported. One of the two methods is supported by each device.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Indicates sampling rates (MSamplingRateVoltage and MSamplingRateTiming) are supported. |
| MIN_VALUE |
0x0 |
Indicates sample count is supported. |
|
[26:26] RW |
GEN5_MARGINING_IND_LEFT_RIGHT_TIMING
MIndLeftRightTiming for 32.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Indicates independent left/right timing margin is supported. |
| MIN_VALUE |
0x0 |
Indicates independent left/right timing margin is not supported. |
|
[25:25] RW |
GEN5_MARGINING_IND_UP_DOWN_VOLTAGE
MIndUpDownVoltage for 32.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Independent up and down voltage margining is supported. |
| MIN_VALUE |
0x0 |
Independent up and down voltage margining is not supported. |
|
[24:24] RW |
GEN5_MARGINING_VOLTAGE_SUPPORTED
MVoltageSupported for 32.0 GT/s for Lane Margining at the Receiver.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1 |
Voltage margining is supported. |
| MIN_VALUE |
0x0 |
Voltage margining is not supported. |
|
[23:21] RO |
RSVDP_21
Reserved for future use.
Reset: hex:0x0;
|
[20:16] RW |
GEN5_MARGINING_MAXLANES
MMaxLanes for 32.0 GT/s for Lane Margining at the Receiver.
Maximum number of Lanes minus 1 that can be margined at the same time. It is recommended that this value be greater than or equal to the number of Lanes in the Link minus 1. Encoding Behavior is undefined if software attempts to margin more than MMaxLanes+1 at the same time.
Note: This value is permitted to exceed the number of Lanes in the Link minus 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x01;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x1f |
Max value. |
| MIN_VALUE |
0x0 |
Min value. |
|
[15:14] RO |
RSVDP_14
Reserved for future use.
Reset: hex:0x0;
|
[13:08] RW |
GEN5_MARGINING_SAMPLE_RATE_TIMING
MSamplingRateTiming for 32.0 GT/s for Lane Margining at the Receiver. The ratio of bits tested to bits received during timing margining. Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The MSamplingRateTiming is fixed to 63 internally.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1f;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x3f |
Value of 63 is a ratio of 64:64 (all bits received). |
| MIN_VALUE |
0x0 |
Value of 0 is a ratio of 1:64 (1 bit of every 64 bits received). |
|
[07:06] RO |
RSVDP_6
Reserved for future use.
Reset: hex:0x0;
|
[05:00] RW |
GEN5_MARGINING_SAMPLE_RATE_VOLTAGE
MSamplingRateVoltage for 32.0 GT/s for Lane Margining at the Receiver. The ratio of bits tested to bits received during voltage margining.
Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The MSamplingRateVoltage is fixed to 63 internally.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x1f;
| Valid Values |
| Name | Value(s) | Description |
| MAX_VALUE |
0x3f |
Value of 63 is a ratio of 64:64 (all bits received). |
| MIN_VALUE |
0x0 |
Value of 0 is a ratio of 1:64 (1 bit of every 64 bits received). |
|
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+0x00000b90 Register(32 bit) PIPE_RELATED_OFF
PIPE Related Register.
This register controls the PIPE's capabitity, control, and status parameters.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000b90 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000058 |
|
|
Unaffected |
0xfffffe00 |
|
|
Undefined |
0xfffffe00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
0 |
| Name |
- |
PIPE_GARBAGE_DATA_MODE |
TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH |
RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH |
| Access |
- |
RW |
RO |
RW |
[08:08] RW |
PIPE_GARBAGE_DATA_MODE
PIPE Garbage Data Mode. - RxValid is de-asserted - a valid RxStartBlock is received at 128b/130b encoding - a valid COM symbol is received at 8b/10b encoding
Note: This register field is sticky.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPLIANT_MODE |
0x0 |
PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is de-asserted. |
| PHY_SUP_MODE |
0x1 |
Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set until when any of the following three conditions are true: |
|
[07:04] RO |
TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH
TXMessageBusMinWriteBufferDepth defined in the PIPE Specification. Indicates the minimum number of write buffer entries that the PHY expects the controller to implement to receive writes from it.
Note: This register field is sticky.
Reset: hex:0x5;
|
[03:00] RW |
RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH
RXMessageBusWriteBufferDepth defined in the PIPE Specification. Indicates the number of write buffer entries that the PHY has implemented to receive writes from the controller. If the value is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the controller issues only write_commited commands, never write_uncommitted.
Note: This register field is sticky.
Reset: hex:0x8;
|
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+0x00000c7c Register(32 bit) DBI_FUNCTION_BANK_CTRL_REG_OFF
DBI Function Bank Control Register.
This register is used to select the PF which is accessable either from lower or upper bank of PFs from DBI.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000c7c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DBI_FUNCTION_BANK_CTRL_REG_RSVD |
DBI_FUNCTION_BANK_CTRL_REG |
| Access |
RO/V |
RW/V |
[31:01] RO/V |
DBI_FUNCTION_BANK_CTRL_REG_RSVD
Reserved.
Reset: hex:0x00000000;
|
[00:00] RW/V |
DBI_FUNCTION_BANK_CTRL_REG
DBI Function Bank Select.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BANK0 |
0x0 |
Functions 0 to 31 are accessible from DBI. |
| BANK1 |
0x1 |
Functions 32 to 63 are accessible from DBI. |
|
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+0x00000c80 Register(32 bit) UTILITY_OFF
UTILITY register (Reserved).
This is a reserved register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000c80 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UTILITY |
| Access |
RW |
[31:00] RW |
UTILITY
Reserved.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00000c88 Register(32 bit) PM_UTILITY_OFF
PM Shadow of UTILITY register (Reserved).
This is the PM shadow copy of the UTILITY register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000c88 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
PM_UTILITY |
| Access |
RO/V |
[31:00] RO/V |
PM_UTILITY
Reserved.
Reset: hex:0x00000000;
|
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+0x00000c8c Register(32 bit) IDE_CTRL_OFF
IDE Control register
Integrity and Data Encryption (IDE) Control register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000c8c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_2 |
EARLY_TDISP_TIMEOUT_DISABLE |
IDE_CTRL_DISABLE |
| Access |
RO |
RW |
RW |
[31:02] RO |
RSVDP_2
Reserved for future use.
Reset: hex:0x00000000;
|
[01:01] RW |
EARLY_TDISP_TIMEOUT_DISABLE
early timeout disable Control Field Must not be toggled during operation.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
When Clear, the TDISP Early Timeout logic is enabled. Received Completions with a TDISP-error are discarded internally by the controller, but the last Completion for a Non-Posted Request discarded for a TDISP-error will trigger an early timeout error associated with such Request. |
| SET |
0x1 |
When Set, the TDISP Early Timeout logic is disabled. Received Completions with a TDISP-error are discarded normally and no early timeout is generated for the associated Non-Posted Requests. |
|
[00:00] RW |
IDE_CTRL_DISABLE
IDE Disable Control Field Must not be toggled during operation.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.
TDISP Prot :WP
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| CLEAR |
0x0 |
When Clear, traffic is passed to IDE logic for encryption (TX) and decryption (RX). |
| SET |
0x1 |
When Set, IDE logic is completely bypassed on the TX and RX datapath and can be powered off. |
|
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+0x00000cac Register(32 bit) PRBS_LOOPBACK_TEST_REG_OFF
PRBS Loopback Test Control Register.
PRBS Loopback Test Control Register located at address 'h5ac in Port Logic.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01000cac at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
RSVDP_17 |
PRBS_LOOPBACK_TEST_UNEXPECTED_FAIL_LANEX |
PRBS_LOOPBACK_TEST_ERROR_COUNTER_LANEX |
PRBS_LOOPBACK_TEST_STARTED_LANEX |
PRBS_LOOPBACK_TEST_LANE_SELECT |
PRBS_LOOPBACK_TEST_FAILED |
PRBS_LOOPBACK_TEST_DONE |
PRBS_LOOPBACK_TEST_ENABLE |
| Access |
RO |
RO/V |
RO/V |
RO/V |
RW |
RO/V |
RW/1C/V |
RW |
[31:17] RO |
RSVDP_17
Reserved for future use.
Reset: hex:0x0000;
|
[16:16] RO/V |
PRBS_LOOPBACK_TEST_UNEXPECTED_FAIL_LANEX
PRBS Loopback Test Unexpected Fail of LaneX. The laneX is defined by "PRBS_LOOPBACK_TEST_LANE_SELECT" register. This will be set when encountering the following cases.
Case1. RXVALID on pipe de-asserts
Case2. Looback finished without receiving idle
Case3. Looback finished without receiving EIOS
This bit is cleared when "PRBS test done" is cleared, or re-entering Loopback.Active state.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[15:08] RO/V |
PRBS_LOOPBACK_TEST_ERROR_COUNTER_LANEX
PRBS Loopback Test Error Counter of LaneX. The laneX is defined by "PRBS_LOOPBACK_TEST_LANE_SELECT" register. When two or more errors occur at one cycle, the counter counts up "1", not "2" or more. These bits are cleared when "PRBS test done" is cleared, or re-entering Loopback.Active state.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:07] RO/V |
PRBS_LOOPBACK_TEST_STARTED_LANEX
PRBS Loopback Test Started of LaneX. The laneX is defined by "PRBS_LOOPBACK_TEST_LANE_SELECT" register. When a first idle data is detected and idle data comparison is started, this register is set to 1. This bit is cleared when "PRBS test done" is cleared, or re-entering Loopback.Active state.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[06:03] RW |
PRBS_LOOPBACK_TEST_LANE_SELECT
Lane Select for PRBS Loopback Test Status. This register is used to select status registers for laneX below.
PRBS_LOOPBACK_STARTED_LANEX : PRBS Loopback started for laneX
PRBS_LOOPBACK_ERR_CNTR_LANEX : PRBS Loopback comparison error counter for laneX
PRBS_LOOPBACK_TEST_UNEXP_FAIL_LANEX : PRBS Loopback unexpected error status for laneX
When this register is set to larger number than number of lanes, the selected status are undefined.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MIN_VAL |
0x0 |
Min value |
| MAX_VAL |
0x0f |
Max value |
|
[02:02] RO/V |
PRBS_LOOPBACK_TEST_FAILED
PRBS Loopback Test Failed.
When 0, the PRBS is done without any error.
When 1, one or more of the following occurred on any lane.
"Compare error(Error Counter !=0)"
"Unexpected Fail"
This bit is cleared when "PRBS test done" is cleared, or re-entering Loopback.Active state)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[01:01] RW/1C/V |
PRBS_LOOPBACK_TEST_DONE
PRBS Loopback Test Done. Set to 1b by controller when exiting from Loopback.Exit. This bit is cleared to 0b by writing it to 1, or re-entering Loopback.Active state
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[00:00] RW |
PRBS_LOOPBACK_TEST_ENABLE
PRBS Loopback Test Enable. When PRBS Loopback TEST is executed, this needs to be set before PORT_LINK_CTRL_OFF.LOOPBACK_ENABLE
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
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+0x00100010 Register(32 bit) BAR0_MASK_REG
BAR$ Mask Register.
This register is the mask for BAR$_REG. If implemented, it exists as a shadow register at the BAR$_REG address.
Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.
Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AXI bridge.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01100010 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x07ffffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
PCI_TYPE0_BAR0_MASK |
PCI_TYPE0_BAR0_ENABLED |
| Access |
WS |
WS |
[31:01] WS |
PCI_TYPE0_BAR0_MASK
- BAR0 Mask.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
Reset: hex:0x03ffffff;
|
[00:00] WS |
PCI_TYPE0_BAR0_ENABLED
- BAR0 Mask Enabled.
Note: This register field is sticky.
Reset: hex:0x1;
|
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+0x00100014 Register(32 bit) BAR1_MASK_REG
BAR1 Mask Register.
This register is the mask for BAR$_REG. If implemented, it exists as a shadow register at the BAR$_REG address.
Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.
Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AXI bridge.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01100014 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0001fffe |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
| Name |
PCI_TYPE0_BAR1_MASK |
PCI_TYPE0_BAR1_ENABLED |
| Access |
WS |
WS |
[31:01] WS |
PCI_TYPE0_BAR1_MASK
- BAR1 Mask.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
Reset: hex:0x0000ffff;
|
[00:00] WS |
PCI_TYPE0_BAR1_ENABLED
- BAR1 Mask Enabled.
Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x00100018 Register(32 bit) BAR2_MASK_REG
BAR2 Mask Register.
This register is the mask for BAR2_REG. If implemented, it exists as a shadow register at the BAR$_REG address.
Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.
Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AXI bridge.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01100018 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x07ffffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
PCI_TYPE0_BAR2_MASK |
PCI_TYPE0_BAR2_ENABLED |
| Access |
WS |
WS |
[31:01] WS |
PCI_TYPE0_BAR2_MASK
BAR2 Mask.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
Reset: hex:0x03ffffff;
|
[00:00] WS |
PCI_TYPE0_BAR2_ENABLED
BAR2 Mask Enabled.
Note: This register field is sticky.
Reset: hex:0x1;
|
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+0x0010001c Register(32 bit) BAR3_MASK_REG
BAR3 Mask Register.
This register is the mask for BAR3_REG. If implemented, it exists as a shadow register at the BAR$_REG address.
Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.
Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AXI bridge.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0110001c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0001fffe |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
| Name |
PCI_TYPE0_BAR3_MASK |
PCI_TYPE0_BAR3_ENABLED |
| Access |
WS |
WS |
[31:01] WS |
PCI_TYPE0_BAR3_MASK
BAR3 Mask.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
Reset: hex:0x0000ffff;
|
[00:00] WS |
PCI_TYPE0_BAR3_ENABLED
BAR3 Mask Enabled.
Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x00100020 Register(32 bit) BAR4_MASK_REG
BAR4 Mask Register.
This register is the mask for BAR4_REG. If implemented, it exists as a shadow register at the BAR$_REG address.
Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.
Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AXI bridge.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01100020 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00007fff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
PCI_TYPE0_BAR4_MASK |
PCI_TYPE0_BAR4_ENABLED |
| Access |
WS |
WS |
[31:01] WS |
PCI_TYPE0_BAR4_MASK
BAR4 Mask.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
Reset: hex:0x00003fff;
|
[00:00] WS |
PCI_TYPE0_BAR4_ENABLED
BAR4 Mask Enabled.
Note: This register field is sticky.
Reset: hex:0x1;
|
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+0x00100024 Register(32 bit) BAR5_MASK_REG
BAR5 Mask Register.
This register is the mask for BAR5_REG. If implemented, it exists as a shadow register at the BAR$_REG address.
Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.
Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of dbi_cs2 when you are using the AXI bridge.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01100024 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00001fff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
PCI_TYPE0_BAR5_MASK |
PCI_TYPE0_BAR5_ENABLED |
| Access |
WS |
WS |
[31:01] WS |
PCI_TYPE0_BAR5_MASK
BAR5 Mask.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
Reset: hex:0x00000fff;
|
[00:00] WS |
PCI_TYPE0_BAR5_ENABLED
BAR5 Mask Enabled.
Note: This register field is sticky.
Reset: hex:0x1;
|
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+0x00100030 Register(32 bit) EXP_ROM_BAR_MASK_REG
Expansion ROM BAR Mask Register.
This register is the mask for EXP_ROM_BASE_ADDR_REG register. If implemented, it exists as a shadow register at EXP_ROM_BAR_MASK_REG address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to this register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01100030 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0001fffe |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
| Name |
ROM_MASK |
ROM_BAR_ENABLED |
| Access |
WS |
WS |
[31:01] WS |
ROM_MASK
Expansion ROM Mask.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if ROM_BAR_ENABLED && ROM_MASK_WRITABLE then W Note: This register field is sticky.
Reset: hex:0x0000ffff;
|
[00:00] WS |
ROM_BAR_ENABLED
Expansion ROM Bar Mask Register Enabled.
Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if ROM_MASK_WRITABLE then W Note: This register field is sticky.
Reset: hex:0x0;
|
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+0x0010007c Register(32 bit) SHADOW_LINK_CAPABILITIES_REG
Shadow Link Capabilities Register.
This is a 6-bit register at the same address as LINK_CAPABILITIES_REG.
The register has only two fields in RTL. All of the other fields here do not exist in RTL and accesses to them are redirected to the corresponding fields in the parent register (LINK_CAPABILITIES_REG).
They are modeled here to make the shadow register (model) 32 bits wide which is a tool requirement.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0110007c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00437c25 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
| Name |
PCIE_CAP_PORT_NUM |
RSVDP_23 |
PCIE_CAP_ASPM_OPT_COMPLIANCE |
PCIE_CAP_LINK_BW_NOT_CAP |
PCIE_CAP_DLL_ACTIVE_REP_CAP |
PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP |
PCIE_CAP_CLOCK_POWER_MAN |
SHADOW_PCIE_CAP_L1_EXIT_LATENCY |
SHADOW_PCIE_CAP_L0S_EXIT_LATENCY |
PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT |
PCIE_CAP_MAX_LINK_WIDTH |
PCIE_CAP_MAX_LINK_SPEED |
| Access |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
[31:24] RO |
PCIE_CAP_PORT_NUM
Shadow Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
Reset: hex:0x00;
|
[23:23] RO |
RSVDP_23
Reserved for future use.
Reset: hex:0x0;
|
[22:22] RO |
PCIE_CAP_ASPM_OPT_COMPLIANCE
Shadow ASPM Optionality Compliance. This field must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.
Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.
Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
Reset: hex:0x1;
|
[21:21] RO |
PCIE_CAP_LINK_BW_NOT_CAP
Shadow Link Bandwidth Notification Capable. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.
This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[20:20] RO |
PCIE_CAP_DLL_ACTIVE_REP_CAP
Shadow Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.
For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.
Reset: hex:0x0;
|
[19:19] RO |
PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP
Shadow Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.
For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.
Note: This register field is sticky.
Reset: hex:0x0;
|
[18:18] RO |
PCIE_CAP_CLOCK_POWER_MAN
Shadow Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) through the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.
L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.
This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.
For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.
For Downstream Ports, the controller hardwires this bit to 0b.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
Reset: hex:0x0;
|
[17:15] RO |
SHADOW_PCIE_CAP_L1_EXIT_LATENCY
Shadow L1 Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request. Common Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R - Dbi2: R/W
Reset: hex:0x6;
|
[14:12] RO |
SHADOW_PCIE_CAP_L0S_EXIT_LATENCY
Shadow L0s Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request. Common Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
Note: The access attributes of this field are as follows: - Wire: R - Dbi: R - Dbi2: R/W
Reset: hex:0x7;
|
[11:10] RO |
PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT
Shadow Level of ASPM (Active State Power Management) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more information on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification. Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| L0S_L1_SUP |
0x3 |
L0s and L1 Supported |
| L0S_SUP |
0x1 |
L0s Supported |
| L1_SUP |
0x2 |
L1 Supported |
| NO_ASPM_SUP |
0x0 |
No ASPM Support |
|
[09:04] RO |
PCIE_CAP_MAX_LINK_WIDTH
Shadow Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width. All encodings other than the defined encodings are reserved. Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x02;
| Valid Values |
| Name | Value(s) | Description |
| X12 |
0x0c |
x12 |
| X1 |
0x1 |
x1 |
| X16 |
0x10 |
x16 |
| X2 |
0x2 |
x2 |
| X4 |
0x4 |
x4 |
| X8 |
0x08 |
x8 |
| X32 |
0x20 |
x32 |
|
[03:00] RO |
PCIE_CAP_MAX_LINK_SPEED
Shadow Maximum Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed. All encodings other than the defined encodings are reserved.
Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
Reset: hex:0x5;
| Valid Values |
| Name | Value(s) | Description |
| SUP_LINK_SPEED_FIELD_BIT_0 |
0x1 |
Supported Link Speeds Vector field bit 0 |
| SUP_LINK_SPEED_FIELD_BIT_1 |
0x2 |
Supported Link Speeds Vector field bit 1 |
| SUP_LINK_SPEED_FIELD_BIT_2 |
0x3 |
Supported Link Speeds Vector field bit 2 |
| SUP_LINK_SPEED_FIELD_BIT_3 |
0x4 |
Supported Link Speeds Vector field bit 3 |
| SUP_LINK_SPEED_FIELD_BIT_4 |
0x5 |
Supported Link Speeds Vector field bit 4 |
| SUP_LINK_SPEED_FIELD_BIT_5 |
0x6 |
Supported Link Speeds Vector field bit 5 |
| SUP_LINK_SPEED_FIELD_BIT_6 |
0x7 |
Supported Link Speeds Vector field bit 6 |
|
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+0x00300000 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_0
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300000 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300004 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_0
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300004 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300008 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300008 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030000c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130000c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300010 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_0
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300010 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300014 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300014 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300018 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300018 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300100 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_0
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300100 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300104 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_0
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300104 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
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+0x00300108 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_0
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300108 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030010c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_0
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130010c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300110 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_0
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300110 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300114 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_0
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300114 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00300200 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_1
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300200 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300204 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_1
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300204 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300208 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300208 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030020c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130020c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300210 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_1
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300210 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300214 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300214 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300218 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300218 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300300 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_1
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300300 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300304 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_1
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300304 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300308 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_1
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300308 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030030c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_1
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130030c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300310 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_1
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300310 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300314 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_1
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300314 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00300400 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_2
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300400 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300404 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_2
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300404 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300408 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300408 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030040c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130040c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300410 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_2
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300410 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300414 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300414 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300418 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300418 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300500 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_2
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300500 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300504 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_2
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300504 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300508 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_2
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300508 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030050c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_2
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130050c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300510 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_2
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300510 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300514 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_2
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300514 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00300600 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_3
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300600 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300604 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_3
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300604 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300608 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300608 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030060c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130060c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300610 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_3
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300610 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300614 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300614 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300618 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300618 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300700 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_3
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300700 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300704 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_3
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300704 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300708 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_3
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300708 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030070c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_3
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130070c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300710 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_3
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300710 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300714 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_3
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300714 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00300800 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_4
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300800 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300804 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_4
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300804 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300808 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300808 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030080c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130080c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300810 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_4
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300810 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300814 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300814 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300818 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300818 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300900 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_4
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300900 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300904 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_4
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300904 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300908 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_4
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300908 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030090c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_4
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130090c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300910 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_4
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300910 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300914 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_4
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300914 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00300a00 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_5
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300a00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300a04 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_5
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300a04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300a08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300a08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00300a0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300a0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300a10 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_5
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300a10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300a14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300a14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300a18 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300a18 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300b00 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_5
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300b00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300b04 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_5
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300b04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300b08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_5
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300b08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00300b0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_5
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300b0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300b10 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_5
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300b10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300b14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_5
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300b14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00300c00 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_6
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300c00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300c04 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_6
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300c04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300c08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300c08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00300c0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300c0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300c10 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_6
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300c10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300c14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300c14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300c18 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300c18 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300d00 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_6
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300d00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300d04 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_6
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300d04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300d08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_6
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300d08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00300d0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_6
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300d0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300d10 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_6
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300d10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300d14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_6
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300d14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00300e00 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_7
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300e00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300e04 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_7
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300e04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300e08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300e08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00300e0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300e0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300e10 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_7
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300e10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00300e14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300e14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300e18 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300e18 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300f00 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_7
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300f00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300f04 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_7
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300f04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00300f08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_7
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300f08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00300f0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_7
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300f0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00300f10 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_7
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300f10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00300f14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_7
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01300f14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301000 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_8
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301000 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301004 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_8
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301004 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301008 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_8
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301008 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030100c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_8
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130100c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301010 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_8
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301010 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301014 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_8
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301014 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301018 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_8
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301018 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301100 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_8
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301100 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301104 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_8
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301104 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301108 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_8
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301108 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030110c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_8
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130110c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301110 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_8
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301110 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00301114 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_8
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301114 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301200 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_9
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301200 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301204 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_9
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301204 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301208 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_9
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301208 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030120c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_9
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130120c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301210 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_9
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301210 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301214 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_9
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301214 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301218 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_9
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301218 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301300 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_9
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301300 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301304 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_9
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301304 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301308 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_9
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301308 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030130c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_9
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130130c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301310 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_9
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301310 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00301314 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_9
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301314 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301400 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_10
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301400 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301404 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_10
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301404 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301408 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_10
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301408 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030140c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_10
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130140c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301410 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_10
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301410 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301414 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_10
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301414 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301418 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_10
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301418 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301500 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_10
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301500 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301504 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_10
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301504 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301508 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_10
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301508 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030150c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_10
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130150c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301510 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_10
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301510 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00301514 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_10
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301514 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301600 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_11
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301600 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301604 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_11
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301604 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301608 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_11
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301608 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030160c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_11
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130160c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301610 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_11
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301610 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301614 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_11
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301614 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301618 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_11
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301618 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301700 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_11
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301700 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301704 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_11
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301704 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301708 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_11
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301708 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030170c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_11
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130170c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301710 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_11
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301710 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00301714 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_11
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301714 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301800 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_12
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301800 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301804 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_12
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301804 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301808 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_12
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301808 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030180c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_12
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130180c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301810 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_12
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301810 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301814 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_12
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301814 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301818 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_12
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301818 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301900 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_12
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301900 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301904 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_12
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301904 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301908 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_12
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301908 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030190c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_12
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130190c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301910 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_12
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301910 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00301914 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_12
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301914 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301a00 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_13
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301a00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301a04 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_13
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301a04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301a08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_13
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301a08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00301a0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_13
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301a0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301a10 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_13
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301a10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301a14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_13
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301a14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
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+0x00301a18 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_13
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301a18 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
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+0x00301b00 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_13
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301b00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301b04 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_13
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301b04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301b08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_13
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301b08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00301b0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_13
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301b0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301b10 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_13
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301b10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
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+0x00301b14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_13
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301b14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301c00 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_14
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301c00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301c04 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_14
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301c04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301c08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_14
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301c08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00301c0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_14
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301c0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301c10 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_14
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301c10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301c14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_14
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301c14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301c18 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_14
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301c18 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301d00 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_14
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301d00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301d04 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_14
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301d04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301d08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_14
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301d08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00301d0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_14
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301d0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301d10 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_14
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301d10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
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+0x00301d14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_14
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301d14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00301e00 Register(32 bit) IATU_REGION_CTRL_1_OFF_OUTBOUND_15
iATU Region Control 1 Register.
This register controls the iATU outbound region access based on the optional iATU outbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301e00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU Region Control 2 Register" is '0', then the function number used in generating the function part of the requester ID (RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0x0 unless multifunction operation in the controller is enabled (CX_NFUNC > 1).
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
This is a reserved field. Do not use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is changed to the value in this register.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301e04 Register(32 bit) IATU_REGION_CTRL_2_OFF_OUTBOUND_15
iATU Region Control 2 Register.
Using this register you can enable/disable the outbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301e04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x47000000 |
|
|
Undefined |
0x47000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
- |
0 |
0 |
0 |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
- |
INVERT_MODE |
CFG_SHIFT_MODE |
DMA_BYPASS |
- |
HEADER_SUBSTITUTE_EN |
INHIBIT_PAYLOAD |
TLP_HEADER_FIELDS_BYPASS |
SNP |
FUNC_BYPASS |
MSB2BITS_TAG |
TAG_SUBSTITUTE_EN |
TAG |
MSG_CODE |
| Access |
RW |
- |
RW |
RW |
RW |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[29:29] RW |
INVERT_MODE
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Mode.
The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP.
This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region of the PCIe configuration space.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[27:27] RW |
DMA_BYPASS
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated.
Note: This field is reserved for the SW product. You must set it to '0'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[23:23] RW |
HEADER_SUBSTITUTE_EN
Header Substitute Enable.
When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. Encodings are as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| FILL_BYTES |
0x1 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. |
| FORM_ADDR |
0x0 |
LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. |
|
[22:22] RW |
INHIBIT_PAYLOAD
Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. Encoding are define as above.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| NO_SUPPORT_FOR_DATA_TLP |
0x1 |
Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. |
| SUPPORT_DATA_TLP |
0x0 |
Fmt[1] =0/1 so that TLPs with or without data can be sent. |
|
[21:21] RW |
TLP_HEADER_FIELDS_BYPASS
TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or, if AMBA is configured, from the AMBA sideband bus (slv_awmisc_info) and not from the corresponding fields of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i or IATU_REGION_CTRL_2_OFF_OUTBOUND_i registers. The header fields are - TC - PH - TH - ST - AT - Attr (IDO, RO and NS).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[20:20] RW |
SNP
Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[19:19] RW |
FUNC_BYPASS
Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Region Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[18:17] RW |
MSB2BITS_TAG
Not used. Reserved for future use.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[16:16] RW |
TAG_SUBSTITUTE_EN
TAG Substitute Enable. When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI MWr to Vendor Defined Msg/MsgD.
Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6) in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Note (CX_10BITS_TAG=1 || CX_14BITS_TAG=1): For 10-bit tags and 14-bit tags, TAG substitution only applies to the 8 least significant bits of the TAG field (bits 7:0 of Byte 4 of the TLP Header). T9 and T8 of the Header are notsubstitued.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[15:08] RW |
TAG
TAG.
The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
[07:00] RW |
MSG_CODE
MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register.
Memory TLPs: (ST: Steering Tag). When the ST field of an outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space; then the ST field of the TLP is changed to the value in this register. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301e08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_OUTBOUND_15
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301e08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00301e0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_15
iATU Upper Base Address Register.
This register holds the upper 32-bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301e0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space, this register is not used and therefore writing to this register has no effect.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301e10 Register(32 bit) IATU_LIMIT_ADDR_OFF_OUTBOUND_15
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301e10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000ffff |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RO |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RO |
CBUF_INCR
Circular Buffer.
Note: This register field is sticky.
Reset: hex:0xf;
|
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+0x00301e14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_15
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region, or the outbound TLP header information, depending on the setting of HEADER_SUBSTITUTE_EN field of IATU_REGION_CTRL_2_VIEWPORT_OFF_OUTBOUND_i register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301e14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW_OUTBOUND |
| Access |
RW |
[31:00] RW |
LWR_TARGET_RW_OUTBOUND
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so the lower bits of the start address of the new address of the translated region (bits n-1:0) are always '0'). - n is log2(CX_ATU_MIN_REGION_SIZE). When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where the controller determines the content of bytes 12 to 15 of the TLP header.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
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+0x00301e18 Register(32 bit) IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_15
iATU Upper Target Address Register.
This register holds the upper 32 bits of the start address (Upper Target part) of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301e18 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_TARGET_RW |
| Access |
RW |
[31:00] RW |
UPPER_TARGET_RW
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301f00 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_15
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301f00 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301f04 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_15
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301f04 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00301f08 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_15
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301f08 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x00301f0c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_15
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301f0c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00301f10 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_15
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301f10 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00301f14 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_15
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01301f14 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00302100 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_16
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302100 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302104 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_16
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302104 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302108 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_16
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302108 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030210c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_16
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130210c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00302110 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_16
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302110 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00302114 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_16
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302114 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00302300 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_17
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302300 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302304 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_17
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302304 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302308 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_17
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302308 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030230c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_17
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130230c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00302310 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_17
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302310 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00302314 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_17
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302314 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00302500 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_18
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302500 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302504 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_18
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302504 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302508 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_18
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302508 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030250c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_18
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130250c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
|
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+0x00302510 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_18
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302510 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
|
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+0x00302514 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_18
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302514 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00302700 Register(32 bit) IATU_REGION_CTRL_1_OFF_INBOUND_19
iATU Region Control 1 Register.
This register controls the iATU inbound region access based on the optional iATU inbound features enabled using iATU Region Control 2 Register.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302700 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xff8fd800 |
|
|
Undefined |
0xff8fd800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
CTRL_1_FUNC_NUM |
- |
INCREASE_REGION_SIZE |
- |
ATTR |
TD |
TC |
TYPE |
| Access |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
[22:20] RW |
CTRL_1_FUNC_NUM
Function Number.
MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
CFG0/CFG1: When the destination function number as specified in the routing ID of the TLP header matches the function, then address translation proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[13:13] RW |
INCREASE_REGION_SIZE
Increase the maximum ATU Region size. When set, the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear, the maximum ATU Region size is 4 GB (default).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Maximum ATU Region size is 4 GB (default) |
| ENABLE |
0x1 |
Maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE |
|
[10:09] RW |
ATTR
When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "ATTR Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[08:08] RW |
TD
When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[07:05] RW |
TC
When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit of the "iATU Region Control 2 Register" is set.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
|
[04:00] RW |
TYPE
When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful).
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302704 Register(32 bit) IATU_REGION_CTRL_2_OFF_INBOUND_19
iATU Region Control 2 Register.
Using this register you can enable/disable the inbound iATU optional features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302704 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0x04561800 |
|
|
Undefined |
0x04561800 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
- |
0 |
0 |
0 |
- |
0 |
- |
0 |
- |
- |
0 |
0 |
0 |
0 |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
REGION_EN |
MATCH_MODE |
INVERT_MODE |
CFG_SHIFT_MODE |
FUZZY_TYPE_MATCH_CODE |
- |
RESPONSE_CODE |
SINGLE_ADDR_LOC_TRANS_EN |
- |
MSG_CODE_MATCH_EN |
- |
FUNC_NUM_MATCH_EN |
- |
ATTR_MATCH_EN |
TD_MATCH_EN |
TC_MATCH_EN |
MSG_TYPE_MATCH_MODE |
- |
BAR_NUM |
MSG_CODE |
| Access |
RW |
RW |
RW |
RW |
RW |
- |
RW |
RW |
- |
RW |
- |
RW |
- |
RW |
RW |
RW |
RW |
- |
RW |
RW |
[31:31] RW |
REGION_EN
Region Enable. This bit must be set to '1' for address translation to take place.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[30:30] RW |
MATCH_MODE
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows:
For MEM I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers must be setup. - 1: BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header, but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The lower Base and Limit Register should be programmed to translate TLPs based on vendor specific information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND MSG_TYPE_MATCH_MODE =1, then Match Mode is ignored.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| ONE |
0x1 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
| ZERO |
0x0 |
The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. |
|
[29:29] RW |
INVERT_MODE
Invert Mode Enable. When set the address matching region is inverted. Therefore, an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). When set all regions of that type must use address match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Invert Mode Disable |
| ENABLE |
0x1 |
Invert Mode Enable |
|
[28:28] RW |
CFG_SHIFT_MODE
CFG Shift Enable. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of your application memory space using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
CFG Shift Disable |
| ENABLE |
0x1 |
CFG Shift Enable |
|
[27:27] RW |
FUZZY_TYPE_MATCH_CODE
Fuzzy Type Match Enable. When enabled, the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd, and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap, and CAS are seen as identical. For example, CFG0 in the TYPE field in the "iATU Region Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Fuzzy Type Match Disable |
| ENABLE |
0x1 |
Fuzzy Type Match Enable |
|
[25:24] RW |
RESPONSE_CODE
Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| COMPL_ABORT |
0x2 |
Completer abort (CA) |
| NORMAL_RADM |
0x0 |
Normal RADM filter response is used. |
| NOT_USED |
0x3 |
Not used / undefined / reserved |
| UNSUP_REQ |
0x1 |
Unsupported request (UR) |
|
[23:23] RW |
SINGLE_ADDR_LOC_TRANS_EN
Single Address Location Translate Enable.
When enabled, Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the AXI bridge is enabled.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[21:21] RW |
MSG_CODE_MATCH_EN
Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the "iATU Region Control 2 Register") occurs (in MSG transactions) for address translation to proceed.
ST Match Enable (Mem TLPs). Ensures that a successful ST TLP field comparison match (see ST field of the "iATU Region Control 2 Register") occurs (in MEM transactions) for address translation to proceed. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Virtual Function Number Match Disable |
| ENABLE |
0x1 |
Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) |
|
[19:19] RW |
FUNC_NUM_MATCH_EN
Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the "iATU Region Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Function Number Match Disable |
| ENABLE |
0x1 |
Function Number Match Enable |
|
[16:16] RW |
ATTR_MATCH_EN
ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
ATTR Match Disable |
| ENABLE |
0x1 |
ATTR Match Enable |
|
[15:15] RW |
TD_MATCH_EN
TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TD Match Disable |
| ENABLE |
0x1 |
TD Match Enable |
|
[14:14] RW |
TC_MATCH_EN
TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU Region Control 1 Register") occurs for address translation to proceed.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
TC Match Disable |
| ENABLE |
0x1 |
TC Match Enable |
|
[13:13] RW |
MSG_TYPE_MATCH_MODE
Message Type Match Mode. When enabled, and if single address location translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the IATU_REGION_CTRL_1_VIEWPORT_OFF_INBOUND_i register (TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages when AXI bridge is configured on client interface.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DISABLE |
0x0 |
Disable |
| ENABLE |
0x1 |
Enable |
|
[10:08] RW |
BAR_NUM
BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal internal BAR address matching mechanism " is the same as this field, address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Match Mode" bit of the "iATU Region Control 2 Register" is set. IO translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that BAR configured as an IO BAR.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| BAR0 |
0x0 |
BAR0 |
| BAR1 |
0x1 |
BAR1 |
| BAR2 |
0x2 |
BAR2 |
| BAR3 |
0x3 |
BAR3 |
| BAR4 |
0x4 |
BAR4 |
| BAR5 |
0x5 |
BAR5 |
| ROM |
0x6 |
ROM |
| RSVD |
0x7 |
reserved |
|
[07:00] RW |
MSG_CODE
MSG TLPs: (Message Code). When the MSG_CODE field of an inbound Msg/MsgD TLP is matched to this value, then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU Region Control 2 Register" is set and the TYPE field of the inbound TLP is Msg/MsgD.
Memory TLPs: (ST: Steering Tag). When the ST field of an inbound TLP is matched to this value, then address translation proceeds. This check is only performed if the "ST Match Enable" bit of the "iATU Region Control 2 Register" is set. The setting is independent of the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is '1'.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00;
|
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+0x00302708 Register(32 bit) IATU_LWR_BASE_ADDR_OFF_INBOUND_19
iATU Lower Base Address Register.
The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB, 8 kB, 16 kB, 32 kB, 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For example, if set to 64 kB; the lower 16 bits of the Base, Limit and Target registers are zero and all address regions are aligned on 64 kB boundaries. More precisely, the lower log2(CX_ATU_MIN_REGION_SIZE) bits are zero.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302708 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_BASE_RW |
LWR_BASE_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_BASE_RW
Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE)
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_BASE_HW
Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
n is log2(CX_ATU_MIN_REGION_SIZE)
Reset: hex:0x0000;
|
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+0x0030270c Register(32 bit) IATU_UPPER_BASE_ADDR_OFF_INBOUND_19
iATU Upper Base Address Register.
This register holds the upper 32 bits of the start (and end) address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0130270c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
UPPER_BASE_RW |
| Access |
RW |
[31:00] RW |
UPPER_BASE_RW
Forms bits [63:32] of the start (and end) address of the address region to be translated.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x00000000;
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+0x00302710 Register(32 bit) IATU_LIMIT_ADDR_OFF_INBOUND_19
iATU Limit Address Register.
This register holds the end address of the address region to be translated.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302710 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x0000fff0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| Name |
LIMIT_ADDR_RW |
LIMIT_ADDR_HW |
CBUF_INCR |
| Access |
RW |
RO |
RW |
[31:16] RW |
LIMIT_ADDR_RW
Forms upper bits of the end address of the address region to be translated. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms the upper bits of the limit address for the circular buffer.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:04] RO |
LIMIT_ADDR_HW
Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary, so these bits are always all ones. When SINGLE_ADDR_LOC_TRANS_EN = 1, MSG_TYPE_MATCH_MODE = 1, and CBUF_INCR > 0 then this field forms lower bits of the limit address for the circular buffer. A write to this location is ignored by the PCIe controller.
Note: This register field is sticky.
Reset: hex:0xfff;
|
[03:00] RW |
CBUF_INCR
Circular Buffer Increment. When CX_ATU_SLOC_CBUF = 0, then this field is Read-only and forms the lowest bits of the end address of the address region to be translated. When CX_ATU_SLOC_CBUF = 1, then this field is R/W and forms the upper bits of the Circular Buffer Increment size (CBUF_INCR) field for Single Location Address translation. The increment value (in bytes) is decoded as follows: Note: A write to any bit in the CBUF_INCR field resets the circular buffer pointer - that is, the next matched received Message will be translated to the start address of the Circular Buffer. This field must be written to AFTER the target and limit registers have been updated.
Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Def_0 |
0x0 |
0 (Default; legacy Single Address Location mode) |
| addr_1024 |
0x09 |
1024 |
| addr_128 |
0x6 |
128 |
| addr_16 |
0x3 |
16 |
| addr_2048 |
0x0a |
2048 |
| addr_256 |
0x7 |
256 |
| addr_32 |
0x4 |
32 |
| addr_4 |
0x1 |
4 |
| addr_4096 |
0x0b |
4096 |
| addr_512 |
0x08 |
512 |
| addr_64 |
0x5 |
64 |
| addr_8 |
0x2 |
8 |
| addr_8132 |
0x0c |
8192 |
| addr_rvd1 |
0x0d |
rsvd. |
| addr_rvd2 |
0x0e |
rsvd. |
| addr_rvd3 |
0x0f |
rsvd. |
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+0x00302714 Register(32 bit) IATU_LWR_TARGET_ADDR_OFF_INBOUND_19
iATU Lower Target Address Register.
This register holds the Lower Target part of the new address of the translated region.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01302714 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
LWR_TARGET_RW |
LWR_TARGET_HW |
| Access |
RW |
RO |
[31:16] RW |
LWR_TARGET_RW
Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Note: This register field is sticky.
TDISP Prot :WDB
Reset: hex:0x0000;
|
[15:00] RO |
LWR_TARGET_HW
Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.
A write to this location is ignored by the PCIe controller. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match mode.
Reset: hex:0x0000;
|
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+0x00380000 Register(32 bit) HDMA_EN_OFF_WRCH_0
HDMA Write Channel Enable Register.
This register enables an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380000 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffe |
|
|
Undefined |
0xfffffffe |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
| Name |
- |
ENABLE |
| Access |
- |
RW |
[00:00] RW |
ENABLE
HDMA Write Channel Enable. The controller checks this field for power management purposes. If this field is enabled for any one of the read, or write channel, the controller exits low power state.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
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+0x00380004 Register(32 bit) HDMA_DOORBELL_OFF_WRCH_0
HDMA Write Channel Doorbell Register.
This register controls the Doorbell state of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380004 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
DB_STOP |
DB_START |
| Access |
- |
WS/V |
WS/V |
[01:01] WS/V |
DB_STOP
HDMA Write Channel Doorbell Stop. You must set this field to stop the write transfer for this channel. HDMA stops the write transfer for this channel at the earliest when this field is set.
Note: Only after the HDMA_STATUS_OFF_WRCH_i.STATUS =0x03, you can consider this channel to be in stop state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
[00:00] WS/V |
DB_START
HDMA Write Channel Doorbell Start. You must set this field to start the write transfer for this channel.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
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+0x00380008 Register(32 bit) HDMA_ELEM_PF_OFF_WRCH_0
HDMA Write Channel Prefetch Register.
This register holds information regarding descriptor prefetch of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380008 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ELEMENT_PREFETCH |
| Access |
- |
RW/V |
[06:00] RW/V |
ELEMENT_PREFETCH
This field controls the number of linked list elements (descriptors) this HDMA write channel prefetches. The linked list element pointer loaded by HDMA updates this field.
Note: The actual prefetch value is ELEMENT_PREFETCH plus '1'. For example, if ELEMENT_PREFETCH =0, one descriptor is prefetched by this channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| Max_Val |
0x7f |
The maximum value of ELEMENT_PREFETCH must be <=HDMA_QOS_OFF_WRCH_i.PF_DEPTH |
| Min_Val |
0x0 |
Min Val |
|
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+0x00380010 Register(32 bit) HDMA_LLP_LOW_OFF_WRCH_0
HDMA Write Channel Linked List Pointer Low Register.
This register holds the lower 32 bits of the address of a write channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380010 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_LOW
Lower 32 bits of the address of the transfer list in the local memory. Used in linked list mode only.HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_WRCH* and HDMA_QOS_OFF_WRCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it.A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380014 Register(32 bit) HDMA_LLP_HIGH_OFF_WRCH_0
HDMA Write Channel Linked List Pointer High Register.
This register holds the higher 32 bits of the address of a write channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380014 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_HIGH
Higher 32 bits of the address of the transfer list in the local memory. HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_WRCH* and HDMA_QOS_OFF_WRCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it. A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380018 Register(32 bit) HDMA_CYCLE_OFF_WRCH_0
HDMA Write Channel Producer-Consumer Cycle Synchronization Register.
This register is used to synchronize the producer (software) and the consumer (HDMA) (used in linked list mode only). For more information, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization" in the Databook.
Note: The HDMA updates this register while operating on a linked list.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380018 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
CYCLE_STATE |
CYCLE_BIT |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
CYCLE_STATE
Consumer Cycle State. You must initialize this field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[00:00] RW/V |
CYCLE_BIT
Toggle Cycle Bit.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x0038001c Register(32 bit) HDMA_XFERSIZE_OFF_WRCH_0
HDMA Write Channel Transfer Size Register.
This register holds the transfer size of an HDMA channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138001c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
XFERSIZE |
| Access |
RW/V |
[31:00] RW/V |
XFERSIZE
HDMA Write Channel Transfer Size. You program this register with the size of the HDMA transfer. The maximum HDMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). HDMA automatically decrements the value of this field as the write channel transfer progresses. This field indicates the number of bytes remaining to be requested. When all bytes are requested the current transfer size is zero. In LL mode, the HDMA overwrites this register with the corresponding dword of the LL element.
You can read this register to monitor the transfer progress, but it is not reliable for that specific usage, as it is updated after read requests and not after write requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380020 Register(32 bit) HDMA_SAR_LOW_OFF_WRCH_0
HDMA Write Channel SAR Low Register.
This register holds the lower 32 bits of the Source Address Register (SAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380020 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_LOW
Source Address Register (lower 32 bits). Indicates the address of the local memory from which HDMA reads. The HDMA increments the SAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The SAR is the address of the local memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380024 Register(32 bit) HDMA_SAR_HIGH_OFF_WRCH_0
HDMA Write Channel SAR High Register.
This register holds the higher 32 bits of the Source Address Register (SAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380024 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_HIGH
Source Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380028 Register(32 bit) HDMA_DAR_LOW_OFF_WRCH_0
HDMA Write Channel DAR Low Register.
This register holds the lower 32 bits of the Destination Address Register (DAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380028 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_LOW
Destination Address Register (lower 32 bits). Indicates the address to which HDMA writes. The HDMA increments the DAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The DAR is the address of the remote memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038002c Register(32 bit) HDMA_DAR_HIGH_OFF_WRCH_0
HDMA Write Channel DAR High Register.
This register holds the higher 32 bits of the Destination Address Register (DAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138002c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_HIGH
Destination Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380030 Register(32 bit) HDMA_WATERMARK_EN_OFF_WRCH_0
HDMA Write Channel Linked-list Watermark Enable Register.
This register controls the watermark interrupts generated after processing a watermarked LL element. HDMA updates this field as LL elements are processed.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380030 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
LWIE |
RWIE |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
LWIE
Enables Local Interrupts at watermark events (end of linked list element) in an HDMA write channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
[00:00] RW/V |
RWIE
Enables Remote Interrupts at watermark events (end of linked list element) in an HDMA write channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380034 Register(32 bit) HDMA_CONTROL1_OFF_WRCH_0
HDMA Write Channel Control Settings 1 Register.
This register controls the operation of the HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380034 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffe00 |
|
|
Undefined |
0xfffffe00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
T_BIT_SRC |
T_BIT |
AT |
RO |
DST_SNOOP |
SRC_SNOOP |
MEM_TYPE |
LLEN |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[08:08] RW |
T_BIT_SRC
Completion to Memory Write T-bit source. The HDMA Write channel uses this field to overwrite the T-bit from the application completion interface by the T_BIT field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Enable |
0x1 |
Overwrite the application completion interface T-bit by the T_BIT field value. |
| Disable |
0x0 |
Forward the T-bit as-is. |
|
[07:07] RW |
T_BIT
T-bit TLP Header Bit. Used in the IDE Prefix for IDE TLPs to indicate that DMA TLP is part of a trusted execution environment. The HDMA write channel uses this TLP header field when generating MRD/IMWr TLP requests.
When T_BIT_SRC field is set to 0x1, the HDMA uses this TLP header field when generating MWr TLP requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[06:05] RW |
AT
Address Translation Services TLP Header Bit (AT). The HDMA write channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[04:04] RW |
RO
Relaxed Ordering TLP Header Bit. HDMA write channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[03:03] RW |
DST_SNOOP
Destination No Snoop TLP Header Bit. The HDMA write channel uses this TLP header field when generating MWr/IMWr (DAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[02:02] RW |
SRC_SNOOP
Source No Snoop TLP Header Bit. The HDMA write channel uses this TLP header field when generating MRd (SAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[01:01] RW |
MEM_TYPE
Master AXI ACE-Lite Cache Coherency Control. This field sets the HDMA write channel memory type of the address space of the data transfer as follows: For more information, see "ACE-Lite Features and Limitations" section of the Databook. Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MEM_TYPE |
0x1 |
memory type |
| PERIPHERAL |
0x0 |
peripheral type |
|
[00:00] RW |
LLEN
This field enables the HDMA write channel Linked List mode.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380038 Register(32 bit) HDMA_FUNC_NUM_OFF_WRCH_0
HDMA Write Channel Function Number Register.
This register controls HDMA write channel to Physical/Virtual function mapping.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380038 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffffe0 |
|
|
Undefined |
0xffffffe0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
PF |
| Access |
- |
RW |
[04:00] RW |
PF
DMA Channel Physical Function Number.
DMA channel wide physical function of the generated TLP. The controller uses this field to form the requester ID for requests. Function numbering starts at '0'. When you have enabled SR-IOV, refer to VF and VF_EN fields of this register as well. The behavior is undefined if any value outside of the valid range is set to this field.
At the signal interfaces, DMA drives the XADM / RADM signals d_client[0|1]_tlp_func_num / d_radm_trgt1_func_num.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
|
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+0x0038003c Register(32 bit) HDMA_QOS_OFF_WRCH_0
HDMA Write Channel QoS Settings Register.
This register controls the HDMA write channel QoS features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138003c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00030008 |
|
|
Unaffected |
0xfc00ff00 |
|
|
Undefined |
0xfc00ff00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
| Name |
- |
PF_DEPTH |
- |
WEIGHT |
TC |
| Access |
- |
RW |
- |
RW |
RW |
[25:16] RW |
PF_DEPTH
This field controls the linked list prefetch allocation space for an HDMA write channel. Each write channel stores PF_DEPTH plus '1' linked list elements. For example, if PF_DEPTH =0, the write channel stores one linked list element. This field must be within the range: [ 0 : floor(CX_DMA_WR_LLQ * CC_NUM_DMA_WR_CHAN / number_of_active_channels) - 1 ].
Note:
If this field is set to a value outside the specified range, data corruption or channel crosstalk may happen.
If PF_DEPTH is changed at run time, only channels in the range: [ 0 : number_of_active_channels - 1 ] can be doorbelled.
This field cannot be changed while any write engine channel is in doorbell state. Doing so might yield undefined results.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x003;
|
[07:03] RW |
WEIGHT
Reserved.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x01;
|
[02:00] RW |
TC
Traffic Class TLP Header Field (TC). The HDMA write channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x00380080 Register(32 bit) HDMA_STATUS_OFF_WRCH_0
HDMA Write Channel Status Register.
This register specifies the current operational state of a channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380080 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000003 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
| Name |
- |
STATUS |
| Access |
- |
RO/V |
[01:00] RO/V |
STATUS
HDMA Write Channel Status.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| ABORTED |
0x2 |
An error condition is detected, and the HDMA has stopped this channel. ERROR field of the HDMA_INT_STATUS_OFF_WRCH_0 register specifies the error. |
| RESERVED |
0x0 |
Reserved |
| RUNNING |
0x1 |
This channel is active and transferring data. |
| STOPPED |
0x3 |
The HDMA has transferred all data for this channel. |
|
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+0x00380084 Register(32 bit) HDMA_INT_STATUS_OFF_WRCH_0
HDMA Write Channel Interrupt Status Register.
This register provides information regarding the HDMA write channel interrupt status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380084 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ERROR |
ABORT |
WATERMARK |
STOP |
| Access |
- |
RO/V |
RO/V |
RO/V |
RO/V |
[06:03] RO/V |
ERROR
HDMA Write Channel Interrupt Error Status. Specifies the error that caused the HDMA to change HDMA_STATUS_OFF_WRCH_i.STATUS to ABORTED state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
No error to report. This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.ABORT_CLEAR =1 |
| DATA_CPL_TIMEOUT |
0x08 |
CPL timeout while reading data from the source. |
| DATA_CPL_UR |
0x09 |
Unsupported request CPL while reading data from the source. |
| DATA_MWR |
0x0c |
Error response received while writing data to the destination. Only valid for Write Channels with AXI bridge (AMBA_INTERFACE >2). |
| LL_CPL_UR |
0x1 |
Unsupported request CPL while reading a linked list element. |
| DATA_CPL_CA |
0x0a |
Completer abort CPL while reading data from the source. |
| DATA_CPL_EP |
0x0b |
Poisoned data CPL while reading data from the source. Only valid if CC_DMA_ABORT_ON_POISONED is set. |
| LL_CPL_CA |
0x2 |
Completer abort CPL while reading a linked list element. |
| LL_CPL_EP |
0x3 |
Poisoned data CPL while reading a linked list element. |
|
[02:02] RO/V |
ABORT
HDMA Write Channel Abort Interrupt Status. ABORT and STOP register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.ABORT_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_WRCH_i.LAIE =1 and a local interrupt is generated, this field indicates that an error is detected for this channel. |
|
[01:01] RO/V |
WATERMARK
HDMA Write Channel Watermark Interrupt Status.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.WATERMARK_CLEAR =1 |
| Set |
0x1 |
If HDMA_WATERMARK_EN_OFF_WRCH_i.LWIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for an element with the LWIE bit set. |
|
[00:00] RO/V |
STOP
HDMA Write Channel Stop Interrupt Status. STOP and ABORT register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.STOP_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_WRCH_i.LSIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for this channel. |
|
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+0x00380088 Register(32 bit) HDMA_INT_SETUP_OFF_WRCH_0
HDMA Write Channel Interrupt Setup Register.
This register is used to configure interrupts for a write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380088 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000007 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
| Name |
- |
LAIE |
RAIE |
LSIE |
RSIE |
ABORT_MASK |
WATERMARK_MASK |
STOP_MASK |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[06:06] RW |
LAIE
HDMA Write Channel Local Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in abort conditions. |
|
[05:05] RW |
RAIE
HDMA Write Channel Remote Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in abort conditions. |
|
[04:04] RW |
LSIE
HDMA Write Channel Local Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in stop conditions. |
|
[03:03] RW |
RSIE
HDMA Write Channel Remote Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in stop conditions. |
|
[02:02] RW |
ABORT_MASK
HDMA Write Channel Abort Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for abort interrupts. |
|
[01:01] RW |
WATERMARK_MASK
HDMA Write Channel Watermark Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for watermark interrupts. |
|
[00:00] RW |
STOP_MASK
HDMA Write Channel Stop Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for stop interrupts. |
|
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+0x0038008c Register(32 bit) HDMA_INT_CLEAR_OFF_WRCH_0
HDMA Write Channel Interrupt Clear Register.
This register indicates interrupt clear status of a write channel. It is a self-clearing register. Reads to this register returns '0'.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138008c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffff8 |
|
|
Undefined |
0xfffffff8 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
| Name |
- |
ABORT_CLEAR |
WATERMARK_CLEAR |
STOP_CLEAR |
| Access |
- |
WS/V |
WS/V |
WS/V |
[02:02] WS/V |
ABORT_CLEAR
HDMA Abort Channel Abort Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the ABORT and ERROR fields of the HDMA_INT_STATUS_OFF_WRCH_i register. |
| Clear |
0x0 |
Clear |
|
[01:01] WS/V |
WATERMARK_CLEAR
HDMA Write Channel Watermark Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the WATERMARK field of the HDMA_INT_STATUS_OFF_WRCH_i register. |
| Clear |
0x0 |
Clear |
|
[00:00] WS/V |
STOP_CLEAR
HDMA Write Channel Stop Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the STOP field of the HDMA_INT_STATUS_OFF_WRCH_i register. |
| Clear |
0x0 |
Clear |
|
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+0x00380090 Register(32 bit) HDMA_MSI_STOP_LOW_OFF_WRCH_0
HDMA Write Stop Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380090 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Stop Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380094 Register(32 bit) HDMA_MSI_STOP_HIGH_OFF_WRCH_0
HDMA Write Stop Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380094 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Stop Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380098 Register(32 bit) HDMA_MSI_WATERMARK_LOW_OFF_WRCH_0
HDMA Write Watermark Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380098 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Watermark Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038009c Register(32 bit) HDMA_MSI_WATERMARK_HIGH_OFF_WRCH_0
HDMA Write Watermark Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138009c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Watermark Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003800a0 Register(32 bit) HDMA_MSI_ABORT_LOW_OFF_WRCH_0
HDMA Write Abort Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Abort Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013800a0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Abort Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003800a4 Register(32 bit) HDMA_MSI_ABORT_HIGH_OFF_WRCH_0
HDMA Write Abort Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Abort Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013800a4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Abort Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003800a8 Register(32 bit) HDMA_MSI_MSGD_OFF_WRCH_0
HDMA Write Channel Remote Interrupt Data Register.
This register holds the IMWr TLP Data of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013800a8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffff0000 |
|
|
Undefined |
0xffff0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
MSI_MESSAGE |
| Access |
- |
RW |
[15:00] RW |
MSI_MESSAGE
The HDMA write channel uses this field to generate the data field for every IMWr TLPs it generates.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffff |
Max Val |
|
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+0x00380100 Register(32 bit) HDMA_EN_OFF_RDCH_0
HDMA Read Channel Enable.
This register enables an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380100 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffe |
|
|
Undefined |
0xfffffffe |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
| Name |
- |
ENABLE |
| Access |
- |
RW |
[00:00] RW |
ENABLE
HDMA Read Channel Enable. The controller checks this field for power management purposes. If this field is enabled for any one of the read, or write channel, the controller exits low power state.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380104 Register(32 bit) HDMA_DOORBELL_OFF_RDCH_0
HDMA Read Channel Doorbell Register.
This register controls the Doorbell state of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380104 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
DB_STOP |
DB_START |
| Access |
- |
WS/V |
WS/V |
[01:01] WS/V |
DB_STOP
HDMA Read Channel Doorbell Stop. You must set this field to stop the read transfer for this channel. HDMA stops the read transfer for this channel at the earliest when this field is set.
Note: Only after the HDMA_STATUS_OFF_RDCH_i.STATUS =0x03, you can consider this channel to be in stop state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
[00:00] WS/V |
DB_START
HDMA Read Channel Doorbell Start. You must set this field to start the read transfer for this channel.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
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+0x00380108 Register(32 bit) HDMA_ELEM_PF_OFF_RDCH_0
HDMA Read Channel Prefetch Register.
This register holds information regarding descriptor prefetch of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380108 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ELEMENT_PREFETCH |
| Access |
- |
RW/V |
[06:00] RW/V |
ELEMENT_PREFETCH
This field controls the number of linked list elements (descriptors) this HDMA read channel prefetches. The linked list element pointer loaded by HDMA updates this field.
Note: The actual prefetch value is ELEMENT_PREFETCH plus '1'. For example, if ELEMENT_PREFETCH =0, one descriptor is prefetched by this channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| Max_Val |
0x7f |
The maximum value of ELEMENT_PREFETCH must be <=HDMA_QOS_OFF_RDCH_i.PF_DEPTH |
| Min_Val |
0x0 |
Min Val |
|
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+0x00380110 Register(32 bit) HDMA_LLP_LOW_OFF_RDCH_0
HDMA Read Channel Linked List Pointer Low Register.
This register holds the lower 32 bits of the address of a read channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380110 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_LOW
Lower 32 bits of the address of the transfer list in the local memory. Used in linked list mode only. HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_RDCH* and HDMA_QOS_OFF_RDCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it.A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380114 Register(32 bit) HDMA_LLP_HIGH_OFF_RDCH_0
HDMA Read Channel Linked List Pointer High Register.
This register holds the higher 32 bits of the address of a read channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380114 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_HIGH
Higher 32 bits of the address of the transfer list in the local memory. HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_RDCH* and HDMA_QOS_OFF_RDCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it. A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380118 Register(32 bit) HDMA_CYCLE_OFF_RDCH_0
HDMA Read Channel Producer-Consumer Cycle Synchronization Register.
This register is used to synchronize the producer (software) and the consumer (HDMA) (used in linked list mode only). For more information, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization" in the Databook.
Note: The HDMA updates this register while operating on a linked list.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380118 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
CYCLE_STATE |
CYCLE_BIT |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
CYCLE_STATE
Consumer Cycle State. You must initialize this field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[00:00] RW/V |
CYCLE_BIT
Toggle Cycle Bit.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x0038011c Register(32 bit) HDMA_XFERSIZE_OFF_RDCH_0
HDMA Read Channel Transfer Size Register.
This register holds the transfer size of an HDMA channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138011c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
XFERSIZE |
| Access |
RW/V |
[31:00] RW/V |
XFERSIZE
HDMA Read Channel Transfer Size. You program this register with the size of the HDMA transfer. The maximum HDMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). HDMA automatically decrements the value of this field as the read channel transfer progresses. This field indicates the number of bytes remaining to be requested. When all bytes are requested the current transfer size is zero. In LL mode, the HDMA overwrites this register with the corresponding dword of the LL element.
You can read this register to monitor the transfer progress, but it is not reliable for that specific usage, as it is updated after read requests and not after write requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380120 Register(32 bit) HDMA_SAR_LOW_OFF_RDCH_0
HDMA Read Channel SAR Low Register.
This register holds the lower 32 bits of the Source Address Register (SAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380120 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_LOW
Source Address Register (lower 32 bits). Indicates the address of the local memory from which HDMA reads. The HDMA increments the SAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The SAR is the address of the remote memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380124 Register(32 bit) HDMA_SAR_HIGH_OFF_RDCH_0
HDMA Read Channel SAR High Register.
This register holds the higher 32 bits of the Source Address Register (SAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380124 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_HIGH
Source Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380128 Register(32 bit) HDMA_DAR_LOW_OFF_RDCH_0
HDMA Read Channel DAR Low Register.
This register holds the lower 32 bits of the Destination Address Register (DAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380128 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_LOW
Destination Address Register (lower 32 bits). Indicates the address to which HDMA writes. The HDMA increments the DAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The DAR is the address of the local memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038012c Register(32 bit) HDMA_DAR_HIGH_OFF_RDCH_0
HDMA Read Channel DAR High Register.
This register holds the higher 32 bits of the Destination Address Register (DAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138012c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_HIGH
Destination Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380130 Register(32 bit) HDMA_WATERMARK_EN_OFF_RDCH_0
HDMA Read Channel Linked-list Watermark Enable Register.
This register controls the watermark interrupts generated after processing a watermarked LL element. HDMA updates this field as LL elements are processed.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380130 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
LWIE |
RWIE |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
LWIE
Enables Local Interrupts at watermark events (end of linked list element) in an HDMA read channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
[00:00] RW/V |
RWIE
Enables Remote Interrupts at watermark events (end of linked list element) in an HDMA read channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380134 Register(32 bit) HDMA_CONTROL1_OFF_RDCH_0
HDMA Read Channel Control Settings 1 Register.
This register controls the operation of the HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380134 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffe00 |
|
|
Undefined |
0xfffffe00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
T_BIT_SRC |
T_BIT |
AT |
RO |
DST_SNOOP |
SRC_SNOOP |
MEM_TYPE |
LLEN |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[08:08] RW |
T_BIT_SRC
Completion to Memory Write T-bit source. The HDMA read channel uses this field to overwrite the T field of the IDE prefix from the core completions by the T_BIT field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Enable |
0x1 |
Overwrite the T field of the Core completion IDE prefix by the T_BIT field value. |
| Disable |
0x0 |
Forward the T-bit as-is. |
|
[07:07] RW |
T_BIT
T-bit TLP Header Bit. Used in the IDE Prefix for IDE TLPs to indicate that DMA TLP is part of a trusted execution environment. The HDMA read channel uses this TLP header field when generating MRd/IMWr TLP requests.
When T_BIT_SRC field is set to 0x1, the HDMA uses this TLP header field when generating MWr TLP requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[06:05] RW |
AT
Address Translation Services TLP Header Bit (AT). The HDMA read channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[04:04] RW |
RO
Relaxed Ordering TLP Header Bit. HDMA read channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[03:03] RW |
DST_SNOOP
Destination No Snoop TLP Header Bit. The HDMA read channel uses this TLP header field when generating MWr/IMWr (DAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[02:02] RW |
SRC_SNOOP
Source No Snoop TLP Header Bit. The HDMA read channel uses this TLP header field when generating MRd (SAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[01:01] RW |
MEM_TYPE
Master AXI ACE-Lite Cache Coherency Control. This field sets the HDMA read channel memory type of the address space of the data transfer as follows: For more information, see "ACE-Lite Features and Limitations" section of the Databook. Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MEM_TYPE |
0x1 |
memory type |
| PERIPHERAL |
0x0 |
peripheral type |
|
[00:00] RW |
LLEN
This field enables the HDMA read channel Linked List mode.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380138 Register(32 bit) HDMA_FUNC_NUM_OFF_RDCH_0
HDMA Read Channel Function Number Register.
This register controls HDMA read channel to Physical/Virtual function mapping.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380138 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffffe0 |
|
|
Undefined |
0xffffffe0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
PF |
| Access |
- |
RW |
[04:00] RW |
PF
DMA Channel Physical Function Number.
DMA channel wide physical function of the generated TLP. The controller uses this field to form the requester ID for requests. Function numbering starts at '0'. When you have enabled SR-IOV, refer to VF and VF_EN fields of this register as well. The behavior is undefined if any value outside of the valid range is set to this field.
At the signal interfaces, DMA drives the XADM / RADM signals d_client[0|1]_tlp_func_num / d_radm_trgt1_func_num.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
|
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+0x0038013c Register(32 bit) HDMA_QOS_OFF_RDCH_0
HDMA Read Channel QoS Settings Register.
This register controls the HDMA read channel QoS features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138013c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00030008 |
|
|
Unaffected |
0xfc00ff00 |
|
|
Undefined |
0xfc00ff00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
| Name |
- |
PF_DEPTH |
- |
WEIGHT |
TC |
| Access |
- |
RW |
- |
RW |
RW |
[25:16] RW |
PF_DEPTH
This field controls the linked list prefetch allocation space for an HDMA read channel. Each read channel stores PF_DEPTH plus '1' linked list elements. For example, if PF_DEPTH =0, the read channel stores one linked list element. This field must be within the range: [ 0 : floor(CX_DMA_RD_LLQ * CC_NUM_DMA_RD_CHAN / number_of_active_channels) - 1 ].
Note: - If this field is set to a value outside the specified range, data corruption or channel crosstalk may happen. - If PF_DEPTH is changed at run time, only channels in the range: [ 0 : number_of_active_channels - 1 ] can be doorbelled. - This field cannot be changed while any read engine channel is in doorbell state. Doing so might yield undefined results.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x003;
| Valid Values |
| Name | Value(s) | Description |
| Max_Field_value |
0x3ff |
Max value |
| Min_Field_value |
0x0 |
Zero value |
|
[07:03] RW |
WEIGHT
Reserved.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x01;
|
[02:00] RW |
TC
Traffic Class TLP Header Field (TC). The HDMA read channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x00380180 Register(32 bit) HDMA_STATUS_OFF_RDCH_0
HDMA Read Channel Status Register.
This register specifies the current operational state of a channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380180 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000003 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
| Name |
- |
STATUS |
| Access |
- |
RO/V |
[01:00] RO/V |
STATUS
HDMA Read Channel Status.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| ABORTED |
0x2 |
An error condition is detected, and the HDMA has stopped this channel. ERROR field of the HDMA_INT_STATUS_OFF_RDCH_0 register specifies the error. |
| RESERVED |
0x0 |
Reserved |
| RUNNING |
0x1 |
This channel is active and transferring data. |
| STOPPED |
0x3 |
The HDMA has transferred all data for this channel. |
|
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+0x00380184 Register(32 bit) HDMA_INT_STATUS_OFF_RDCH_0
HDMA Read Channel Interrupt Status Register.
This register provides information regarding the HDMA read channel interrupt status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380184 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ERROR |
ABORT |
WATERMARK |
STOP |
| Access |
- |
RO/V |
RO/V |
RO/V |
RO/V |
[06:03] RO/V |
ERROR
HDMA Read Channel Error Interrupt Status. Specifies the error that caused the HDMA to change HDMA_STATUS_OFF_RDCH_i.STATUS to ABORTED state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DATA_CPL_TIMEOUT |
0x08 |
CPL timeout while reading data from the source. Only valid for Read Channels. |
| DATA_CPL_UR |
0x09 |
Unsuported request CPL while reading data from the source. |
| DATA_MWR |
0x0c |
Error response received while writing data to the destination. Only valid for Read Channels with AXI bridge (AMBA_INTERFACE >2). |
| LL_CPL_UR |
0x1 |
Unsuported request CPL while reading a linked list element. |
| NONE |
0x0 |
No error to report. This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.ABORT_CLEAR =1 |
| DATA_CPL_CA |
0x0a |
Completer abort CPL while reading data from the source. |
| DATA_CPL_EP |
0x0b |
Poisoned data CPL while reading data from the source. Only valid if CC_DMA_ABORT_ON_POISONED is set. |
| LL_CPL_CA |
0x2 |
Completer abort CPL while reading a linked list element. |
| LL_CPL_EP |
0x3 |
Poisoned data CPL while reading a linked list element. |
|
[02:02] RO/V |
ABORT
HDMA Read Channel Abort Interrupt Status. ABORT and STOP register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.ABORT_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_RDCH_i.LAIE =1 and a local interrupt is generated, this field indicates that an error is detected for this channel. |
|
[01:01] RO/V |
WATERMARK
HDMA Read Channel Watermark Interrupt Status.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.WATERMARK_CLEAR =1 |
| Set |
0x1 |
If HDMA_WATERMARK_EN_OFF_RDCH_i.LWIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for an element with the LWIE bit set. |
|
[00:00] RO/V |
STOP
HDMA Read Channel Stop Interrupt Status. STOP and ABORT register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.STOP_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_RDCH_i.LSIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for this channel. |
|
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+0x00380188 Register(32 bit) HDMA_INT_SETUP_OFF_RDCH_0
HDMA Read Channel Interrupt Setup Register.
This register is used to configure interrupts for a read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380188 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000007 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
| Name |
- |
LAIE |
RAIE |
LSIE |
RSIE |
ABORT_MASK |
WATERMARK_MASK |
STOP_MASK |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[06:06] RW |
LAIE
HDMA Read Channel Local Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in abort conditions. |
|
[05:05] RW |
RAIE
HDMA Read Channel Remote Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in abort conditions. |
|
[04:04] RW |
LSIE
HDMA Read Channel Local Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in stop conditions. |
|
[03:03] RW |
RSIE
HDMA Read Channel Remote Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in stop conditions. |
|
[02:02] RW |
ABORT_MASK
HDMA Read Channel Abort Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for abort interrupts. |
|
[01:01] RW |
WATERMARK_MASK
HDMA Read Channel Watermark Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for watermark interrupts. |
|
[00:00] RW |
STOP_MASK
HDMA Read Channel Stop Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for stop interrupts. |
|
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+0x0038018c Register(32 bit) HDMA_INT_CLEAR_OFF_RDCH_0
HDMA Read Channel Interrupt Clear Register.
This register indicates interrupt clear status of a read channel. It is a self-clearing register. Reads to this register returns '0'.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138018c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffff8 |
|
|
Undefined |
0xfffffff8 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
| Name |
- |
ABORT_CLEAR |
WATERMARK_CLEAR |
STOP_CLEAR |
| Access |
- |
WS/V |
WS/V |
WS/V |
[02:02] WS/V |
ABORT_CLEAR
HDMA Abort Channel Abort Interrupt Clear. Setting this field clears the ABORT and ERROR fields.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the ABORT and ERROR fields of the HDMA_INT_STATUS_OFF_RDCH_i register. |
| Clear |
0x0 |
Clear |
|
[01:01] WS/V |
WATERMARK_CLEAR
HDMA Read Channel Watermark Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the WATERMARK field of the HDMA_INT_STATUS_OFF_RDCH_i register. |
| Clear |
0x0 |
Clear |
|
[00:00] WS/V |
STOP_CLEAR
HDMA Read Channel Stop Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the STOP field of the HDMA_INT_STATUS_OFF_RDCH_i register. |
| Clear |
0x0 |
Clear |
|
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+0x00380190 Register(32 bit) HDMA_MSI_STOP_LOW_OFF_RDCH_0
HDMA Read Stop Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380190 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Stop Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380194 Register(32 bit) HDMA_MSI_STOP_HIGH_OFF_RDCH_0
HDMA Read Stop Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380194 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Stop Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380198 Register(32 bit) HDMA_MSI_WATERMARK_LOW_OFF_RDCH_0
HDMA Read Watermark Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380198 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Watermark Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038019c Register(32 bit) HDMA_MSI_WATERMARK_HIGH_OFF_RDCH_0
HDMA Read Watermark Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138019c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Watermark Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003801a0 Register(32 bit) HDMA_MSI_ABORT_LOW_OFF_RDCH_0
HDMA Read Abort Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Abort Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013801a0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Abort Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Max_Val |
0x0ffffffff |
Max Va |
| Min_Val |
0x0 |
Min Val |
|
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+0x003801a4 Register(32 bit) HDMA_MSI_ABORT_HIGH_OFF_RDCH_0
HDMA Read Abort Remote Interrupt Address High.
This register holds the higher 32 bits of the Abort Interrupt mwr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013801a4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Abort Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
|
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+0x003801a8 Register(32 bit) HDMA_MSI_MSGD_OFF_RDCH_0
HDMA Read Channel Remote Interrupt Data Register.
This register holds the IMWr TLP Data of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013801a8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffff0000 |
|
|
Undefined |
0xffff0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
MSI_MESSAGE |
| Access |
- |
RW |
[15:00] RW |
MSI_MESSAGE
The HDMA read channel uses this field to generate the data field for every IMWr TLPs it generates.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffff |
Max Val |
|
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+0x00380200 Register(32 bit) HDMA_EN_OFF_WRCH_1
HDMA Write Channel Enable Register.
This register enables an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380200 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffe |
|
|
Undefined |
0xfffffffe |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
| Name |
- |
ENABLE |
| Access |
- |
RW |
[00:00] RW |
ENABLE
HDMA Write Channel Enable. The controller checks this field for power management purposes. If this field is enabled for any one of the read, or write channel, the controller exits low power state.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380204 Register(32 bit) HDMA_DOORBELL_OFF_WRCH_1
HDMA Write Channel Doorbell Register.
This register controls the Doorbell state of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380204 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
DB_STOP |
DB_START |
| Access |
- |
WS/V |
WS/V |
[01:01] WS/V |
DB_STOP
HDMA Write Channel Doorbell Stop. You must set this field to stop the write transfer for this channel. HDMA stops the write transfer for this channel at the earliest when this field is set.
Note: Only after the HDMA_STATUS_OFF_WRCH_i.STATUS =0x03, you can consider this channel to be in stop state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
[00:00] WS/V |
DB_START
HDMA Write Channel Doorbell Start. You must set this field to start the write transfer for this channel.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
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+0x00380208 Register(32 bit) HDMA_ELEM_PF_OFF_WRCH_1
HDMA Write Channel Prefetch Register.
This register holds information regarding descriptor prefetch of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380208 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ELEMENT_PREFETCH |
| Access |
- |
RW/V |
[06:00] RW/V |
ELEMENT_PREFETCH
This field controls the number of linked list elements (descriptors) this HDMA write channel prefetches. The linked list element pointer loaded by HDMA updates this field.
Note: The actual prefetch value is ELEMENT_PREFETCH plus '1'. For example, if ELEMENT_PREFETCH =0, one descriptor is prefetched by this channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| Max_Val |
0x7f |
The maximum value of ELEMENT_PREFETCH must be <=HDMA_QOS_OFF_WRCH_i.PF_DEPTH |
| Min_Val |
0x0 |
Min Val |
|
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+0x00380210 Register(32 bit) HDMA_LLP_LOW_OFF_WRCH_1
HDMA Write Channel Linked List Pointer Low Register.
This register holds the lower 32 bits of the address of a write channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380210 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_LOW
Lower 32 bits of the address of the transfer list in the local memory. Used in linked list mode only.HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_WRCH* and HDMA_QOS_OFF_WRCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it.A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380214 Register(32 bit) HDMA_LLP_HIGH_OFF_WRCH_1
HDMA Write Channel Linked List Pointer High Register.
This register holds the higher 32 bits of the address of a write channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380214 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_HIGH
Higher 32 bits of the address of the transfer list in the local memory. HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_WRCH* and HDMA_QOS_OFF_WRCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it. A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380218 Register(32 bit) HDMA_CYCLE_OFF_WRCH_1
HDMA Write Channel Producer-Consumer Cycle Synchronization Register.
This register is used to synchronize the producer (software) and the consumer (HDMA) (used in linked list mode only). For more information, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization" in the Databook.
Note: The HDMA updates this register while operating on a linked list.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380218 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
CYCLE_STATE |
CYCLE_BIT |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
CYCLE_STATE
Consumer Cycle State. You must initialize this field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[00:00] RW/V |
CYCLE_BIT
Toggle Cycle Bit.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x0038021c Register(32 bit) HDMA_XFERSIZE_OFF_WRCH_1
HDMA Write Channel Transfer Size Register.
This register holds the transfer size of an HDMA channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138021c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
XFERSIZE |
| Access |
RW/V |
[31:00] RW/V |
XFERSIZE
HDMA Write Channel Transfer Size. You program this register with the size of the HDMA transfer. The maximum HDMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). HDMA automatically decrements the value of this field as the write channel transfer progresses. This field indicates the number of bytes remaining to be requested. When all bytes are requested the current transfer size is zero. In LL mode, the HDMA overwrites this register with the corresponding dword of the LL element.
You can read this register to monitor the transfer progress, but it is not reliable for that specific usage, as it is updated after read requests and not after write requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380220 Register(32 bit) HDMA_SAR_LOW_OFF_WRCH_1
HDMA Write Channel SAR Low Register.
This register holds the lower 32 bits of the Source Address Register (SAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380220 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_LOW
Source Address Register (lower 32 bits). Indicates the address of the local memory from which HDMA reads. The HDMA increments the SAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The SAR is the address of the local memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380224 Register(32 bit) HDMA_SAR_HIGH_OFF_WRCH_1
HDMA Write Channel SAR High Register.
This register holds the higher 32 bits of the Source Address Register (SAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380224 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_HIGH
Source Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380228 Register(32 bit) HDMA_DAR_LOW_OFF_WRCH_1
HDMA Write Channel DAR Low Register.
This register holds the lower 32 bits of the Destination Address Register (DAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380228 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_LOW
Destination Address Register (lower 32 bits). Indicates the address to which HDMA writes. The HDMA increments the DAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The DAR is the address of the remote memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038022c Register(32 bit) HDMA_DAR_HIGH_OFF_WRCH_1
HDMA Write Channel DAR High Register.
This register holds the higher 32 bits of the Destination Address Register (DAR) of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138022c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_HIGH
Destination Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380230 Register(32 bit) HDMA_WATERMARK_EN_OFF_WRCH_1
HDMA Write Channel Linked-list Watermark Enable Register.
This register controls the watermark interrupts generated after processing a watermarked LL element. HDMA updates this field as LL elements are processed.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380230 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
LWIE |
RWIE |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
LWIE
Enables Local Interrupts at watermark events (end of linked list element) in an HDMA write channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
[00:00] RW/V |
RWIE
Enables Remote Interrupts at watermark events (end of linked list element) in an HDMA write channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380234 Register(32 bit) HDMA_CONTROL1_OFF_WRCH_1
HDMA Write Channel Control Settings 1 Register.
This register controls the operation of the HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380234 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffe00 |
|
|
Undefined |
0xfffffe00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
T_BIT_SRC |
T_BIT |
AT |
RO |
DST_SNOOP |
SRC_SNOOP |
MEM_TYPE |
LLEN |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[08:08] RW |
T_BIT_SRC
Completion to Memory Write T-bit source. The HDMA Write channel uses this field to overwrite the T-bit from the application completion interface by the T_BIT field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Enable |
0x1 |
Overwrite the application completion interface T-bit by the T_BIT field value. |
| Disable |
0x0 |
Forward the T-bit as-is. |
|
[07:07] RW |
T_BIT
T-bit TLP Header Bit. Used in the IDE Prefix for IDE TLPs to indicate that DMA TLP is part of a trusted execution environment. The HDMA write channel uses this TLP header field when generating MRD/IMWr TLP requests.
When T_BIT_SRC field is set to 0x1, the HDMA uses this TLP header field when generating MWr TLP requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[06:05] RW |
AT
Address Translation Services TLP Header Bit (AT). The HDMA write channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[04:04] RW |
RO
Relaxed Ordering TLP Header Bit. HDMA write channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[03:03] RW |
DST_SNOOP
Destination No Snoop TLP Header Bit. The HDMA write channel uses this TLP header field when generating MWr/IMWr (DAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[02:02] RW |
SRC_SNOOP
Source No Snoop TLP Header Bit. The HDMA write channel uses this TLP header field when generating MRd (SAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[01:01] RW |
MEM_TYPE
Master AXI ACE-Lite Cache Coherency Control. This field sets the HDMA write channel memory type of the address space of the data transfer as follows: For more information, see "ACE-Lite Features and Limitations" section of the Databook. Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MEM_TYPE |
0x1 |
memory type |
| PERIPHERAL |
0x0 |
peripheral type |
|
[00:00] RW |
LLEN
This field enables the HDMA write channel Linked List mode.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380238 Register(32 bit) HDMA_FUNC_NUM_OFF_WRCH_1
HDMA Write Channel Function Number Register.
This register controls HDMA write channel to Physical/Virtual function mapping.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380238 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffffe0 |
|
|
Undefined |
0xffffffe0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
PF |
| Access |
- |
RW |
[04:00] RW |
PF
DMA Channel Physical Function Number.
DMA channel wide physical function of the generated TLP. The controller uses this field to form the requester ID for requests. Function numbering starts at '0'. When you have enabled SR-IOV, refer to VF and VF_EN fields of this register as well. The behavior is undefined if any value outside of the valid range is set to this field.
At the signal interfaces, DMA drives the XADM / RADM signals d_client[0|1]_tlp_func_num / d_radm_trgt1_func_num.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
|
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+0x0038023c Register(32 bit) HDMA_QOS_OFF_WRCH_1
HDMA Write Channel QoS Settings Register.
This register controls the HDMA write channel QoS features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138023c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00030008 |
|
|
Unaffected |
0xfc00ff00 |
|
|
Undefined |
0xfc00ff00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
| Name |
- |
PF_DEPTH |
- |
WEIGHT |
TC |
| Access |
- |
RW |
- |
RW |
RW |
[25:16] RW |
PF_DEPTH
This field controls the linked list prefetch allocation space for an HDMA write channel. Each write channel stores PF_DEPTH plus '1' linked list elements. For example, if PF_DEPTH =0, the write channel stores one linked list element. This field must be within the range: [ 0 : floor(CX_DMA_WR_LLQ * CC_NUM_DMA_WR_CHAN / number_of_active_channels) - 1 ].
Note:
If this field is set to a value outside the specified range, data corruption or channel crosstalk may happen.
If PF_DEPTH is changed at run time, only channels in the range: [ 0 : number_of_active_channels - 1 ] can be doorbelled.
This field cannot be changed while any write engine channel is in doorbell state. Doing so might yield undefined results.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x003;
|
[07:03] RW |
WEIGHT
Reserved.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x01;
|
[02:00] RW |
TC
Traffic Class TLP Header Field (TC). The HDMA write channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x00380280 Register(32 bit) HDMA_STATUS_OFF_WRCH_1
HDMA Write Channel Status Register.
This register specifies the current operational state of a channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380280 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000003 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
| Name |
- |
STATUS |
| Access |
- |
RO/V |
[01:00] RO/V |
STATUS
HDMA Write Channel Status.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| ABORTED |
0x2 |
An error condition is detected, and the HDMA has stopped this channel. ERROR field of the HDMA_INT_STATUS_OFF_WRCH_0 register specifies the error. |
| RESERVED |
0x0 |
Reserved |
| RUNNING |
0x1 |
This channel is active and transferring data. |
| STOPPED |
0x3 |
The HDMA has transferred all data for this channel. |
|
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+0x00380284 Register(32 bit) HDMA_INT_STATUS_OFF_WRCH_1
HDMA Write Channel Interrupt Status Register.
This register provides information regarding the HDMA write channel interrupt status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380284 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ERROR |
ABORT |
WATERMARK |
STOP |
| Access |
- |
RO/V |
RO/V |
RO/V |
RO/V |
[06:03] RO/V |
ERROR
HDMA Write Channel Interrupt Error Status. Specifies the error that caused the HDMA to change HDMA_STATUS_OFF_WRCH_i.STATUS to ABORTED state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
No error to report. This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.ABORT_CLEAR =1 |
| DATA_CPL_TIMEOUT |
0x08 |
CPL timeout while reading data from the source. |
| DATA_CPL_UR |
0x09 |
Unsupported request CPL while reading data from the source. |
| DATA_MWR |
0x0c |
Error response received while writing data to the destination. Only valid for Write Channels with AXI bridge (AMBA_INTERFACE >2). |
| LL_CPL_UR |
0x1 |
Unsupported request CPL while reading a linked list element. |
| DATA_CPL_CA |
0x0a |
Completer abort CPL while reading data from the source. |
| DATA_CPL_EP |
0x0b |
Poisoned data CPL while reading data from the source. Only valid if CC_DMA_ABORT_ON_POISONED is set. |
| LL_CPL_CA |
0x2 |
Completer abort CPL while reading a linked list element. |
| LL_CPL_EP |
0x3 |
Poisoned data CPL while reading a linked list element. |
|
[02:02] RO/V |
ABORT
HDMA Write Channel Abort Interrupt Status. ABORT and STOP register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.ABORT_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_WRCH_i.LAIE =1 and a local interrupt is generated, this field indicates that an error is detected for this channel. |
|
[01:01] RO/V |
WATERMARK
HDMA Write Channel Watermark Interrupt Status.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.WATERMARK_CLEAR =1 |
| Set |
0x1 |
If HDMA_WATERMARK_EN_OFF_WRCH_i.LWIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for an element with the LWIE bit set. |
|
[00:00] RO/V |
STOP
HDMA Write Channel Stop Interrupt Status. STOP and ABORT register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_WRCH_i.STOP_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_WRCH_i.LSIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for this channel. |
|
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+0x00380288 Register(32 bit) HDMA_INT_SETUP_OFF_WRCH_1
HDMA Write Channel Interrupt Setup Register.
This register is used to configure interrupts for a write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380288 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000007 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
| Name |
- |
LAIE |
RAIE |
LSIE |
RSIE |
ABORT_MASK |
WATERMARK_MASK |
STOP_MASK |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[06:06] RW |
LAIE
HDMA Write Channel Local Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in abort conditions. |
|
[05:05] RW |
RAIE
HDMA Write Channel Remote Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in abort conditions. |
|
[04:04] RW |
LSIE
HDMA Write Channel Local Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in stop conditions. |
|
[03:03] RW |
RSIE
HDMA Write Channel Remote Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in stop conditions. |
|
[02:02] RW |
ABORT_MASK
HDMA Write Channel Abort Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for abort interrupts. |
|
[01:01] RW |
WATERMARK_MASK
HDMA Write Channel Watermark Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for watermark interrupts. |
|
[00:00] RW |
STOP_MASK
HDMA Write Channel Stop Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for stop interrupts. |
|
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+0x0038028c Register(32 bit) HDMA_INT_CLEAR_OFF_WRCH_1
HDMA Write Channel Interrupt Clear Register.
This register indicates interrupt clear status of a write channel. It is a self-clearing register. Reads to this register returns '0'.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138028c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffff8 |
|
|
Undefined |
0xfffffff8 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
| Name |
- |
ABORT_CLEAR |
WATERMARK_CLEAR |
STOP_CLEAR |
| Access |
- |
WS/V |
WS/V |
WS/V |
[02:02] WS/V |
ABORT_CLEAR
HDMA Abort Channel Abort Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the ABORT and ERROR fields of the HDMA_INT_STATUS_OFF_WRCH_i register. |
| Clear |
0x0 |
Clear |
|
[01:01] WS/V |
WATERMARK_CLEAR
HDMA Write Channel Watermark Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the WATERMARK field of the HDMA_INT_STATUS_OFF_WRCH_i register. |
| Clear |
0x0 |
Clear |
|
[00:00] WS/V |
STOP_CLEAR
HDMA Write Channel Stop Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the STOP field of the HDMA_INT_STATUS_OFF_WRCH_i register. |
| Clear |
0x0 |
Clear |
|
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+0x00380290 Register(32 bit) HDMA_MSI_STOP_LOW_OFF_WRCH_1
HDMA Write Stop Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380290 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Stop Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380294 Register(32 bit) HDMA_MSI_STOP_HIGH_OFF_WRCH_1
HDMA Write Stop Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380294 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Stop Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380298 Register(32 bit) HDMA_MSI_WATERMARK_LOW_OFF_WRCH_1
HDMA Write Watermark Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380298 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Watermark Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038029c Register(32 bit) HDMA_MSI_WATERMARK_HIGH_OFF_WRCH_1
HDMA Write Watermark Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138029c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Watermark Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003802a0 Register(32 bit) HDMA_MSI_ABORT_LOW_OFF_WRCH_1
HDMA Write Abort Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Abort Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013802a0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Abort Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003802a4 Register(32 bit) HDMA_MSI_ABORT_HIGH_OFF_WRCH_1
HDMA Write Abort Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Abort Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013802a4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Abort Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003802a8 Register(32 bit) HDMA_MSI_MSGD_OFF_WRCH_1
HDMA Write Channel Remote Interrupt Data Register.
This register holds the IMWr TLP Data of an HDMA write channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013802a8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffff0000 |
|
|
Undefined |
0xffff0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
MSI_MESSAGE |
| Access |
- |
RW |
[15:00] RW |
MSI_MESSAGE
The HDMA write channel uses this field to generate the data field for every IMWr TLPs it generates.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffff |
Max Val |
|
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+0x00380300 Register(32 bit) HDMA_EN_OFF_RDCH_1
HDMA Read Channel Enable.
This register enables an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380300 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffe |
|
|
Undefined |
0xfffffffe |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
| Name |
- |
ENABLE |
| Access |
- |
RW |
[00:00] RW |
ENABLE
HDMA Read Channel Enable. The controller checks this field for power management purposes. If this field is enabled for any one of the read, or write channel, the controller exits low power state.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380304 Register(32 bit) HDMA_DOORBELL_OFF_RDCH_1
HDMA Read Channel Doorbell Register.
This register controls the Doorbell state of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380304 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
DB_STOP |
DB_START |
| Access |
- |
WS/V |
WS/V |
[01:01] WS/V |
DB_STOP
HDMA Read Channel Doorbell Stop. You must set this field to stop the read transfer for this channel. HDMA stops the read transfer for this channel at the earliest when this field is set.
Note: Only after the HDMA_STATUS_OFF_RDCH_i.STATUS =0x03, you can consider this channel to be in stop state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
[00:00] WS/V |
DB_START
HDMA Read Channel Doorbell Start. You must set this field to start the read transfer for this channel.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Set |
|
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+0x00380308 Register(32 bit) HDMA_ELEM_PF_OFF_RDCH_1
HDMA Read Channel Prefetch Register.
This register holds information regarding descriptor prefetch of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380308 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ELEMENT_PREFETCH |
| Access |
- |
RW/V |
[06:00] RW/V |
ELEMENT_PREFETCH
This field controls the number of linked list elements (descriptors) this HDMA read channel prefetches. The linked list element pointer loaded by HDMA updates this field.
Note: The actual prefetch value is ELEMENT_PREFETCH plus '1'. For example, if ELEMENT_PREFETCH =0, one descriptor is prefetched by this channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
| Valid Values |
| Name | Value(s) | Description |
| Max_Val |
0x7f |
The maximum value of ELEMENT_PREFETCH must be <=HDMA_QOS_OFF_RDCH_i.PF_DEPTH |
| Min_Val |
0x0 |
Min Val |
|
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+0x00380310 Register(32 bit) HDMA_LLP_LOW_OFF_RDCH_1
HDMA Read Channel Linked List Pointer Low Register.
This register holds the lower 32 bits of the address of a read channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380310 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_LOW
Lower 32 bits of the address of the transfer list in the local memory. Used in linked list mode only. HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_RDCH* and HDMA_QOS_OFF_RDCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it.A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380314 Register(32 bit) HDMA_LLP_HIGH_OFF_RDCH_1
HDMA Read Channel Linked List Pointer High Register.
This register holds the higher 32 bits of the address of a read channel transfer list. It is used in linked list mode only.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380314 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
ELEMENT_LIST_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
ELEMENT_LIST_PTR_HIGH
Higher 32 bits of the address of the transfer list in the local memory. HDMA fetches descriptors from local memory respecting the following patterns: - When the current element is a data element; HDMA increments this field by 6 DWORDs times the prefetch depth. For more information, see registers HDMA_ELEM_PF_OFF_RDCH* and HDMA_QOS_OFF_RDCH* - When the current element is a link element; HDMA overwrites this field with the LL Element Pointer of the next LL element structure. The current fetched memory address pointer is not directly visible in this register, instead HDMA updates this register on the following occurrences: - Watermark interrupt event - Channel Status ABORT event - Channel Status STOP event On a watermark interrupt event this register points to the descriptor's address that triggered it. A channel status STOP or ABORT events are end of transfer events that makes this register point to the next data to transfer after the event.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380318 Register(32 bit) HDMA_CYCLE_OFF_RDCH_1
HDMA Read Channel Producer-Consumer Cycle Synchronization Register.
This register is used to synchronize the producer (software) and the consumer (HDMA) (used in linked list mode only). For more information, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization" in the Databook.
Note: The HDMA updates this register while operating on a linked list.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380318 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
CYCLE_STATE |
CYCLE_BIT |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
CYCLE_STATE
Consumer Cycle State. You must initialize this field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[00:00] RW/V |
CYCLE_BIT
Toggle Cycle Bit.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x0038031c Register(32 bit) HDMA_XFERSIZE_OFF_RDCH_1
HDMA Read Channel Transfer Size Register.
This register holds the transfer size of an HDMA channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138031c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
XFERSIZE |
| Access |
RW/V |
[31:00] RW/V |
XFERSIZE
HDMA Read Channel Transfer Size. You program this register with the size of the HDMA transfer. The maximum HDMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). HDMA automatically decrements the value of this field as the read channel transfer progresses. This field indicates the number of bytes remaining to be requested. When all bytes are requested the current transfer size is zero. In LL mode, the HDMA overwrites this register with the corresponding dword of the LL element.
You can read this register to monitor the transfer progress, but it is not reliable for that specific usage, as it is updated after read requests and not after write requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380320 Register(32 bit) HDMA_SAR_LOW_OFF_RDCH_1
HDMA Read Channel SAR Low Register.
This register holds the lower 32 bits of the Source Address Register (SAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380320 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_LOW
Source Address Register (lower 32 bits). Indicates the address of the local memory from which HDMA reads. The HDMA increments the SAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The SAR is the address of the remote memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380324 Register(32 bit) HDMA_SAR_HIGH_OFF_RDCH_1
HDMA Read Channel SAR High Register.
This register holds the higher 32 bits of the Source Address Register (SAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380324 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
SAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
SAR_PTR_HIGH
Source Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380328 Register(32 bit) HDMA_DAR_LOW_OFF_RDCH_1
HDMA Read Channel DAR Low Register.
This register holds the lower 32 bits of the Destination Address Register (DAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380328 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_LOW |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_LOW
Destination Address Register (lower 32 bits). Indicates the address to which HDMA writes. The HDMA increments the DAR as the HDMA transfer progresses. In LL mode, the HDMA overwrites this field with the corresponding dword of the LL element. The DAR is the address of the local memory.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038032c Register(32 bit) HDMA_DAR_HIGH_OFF_RDCH_1
HDMA Read Channel DAR High Register.
This register holds the higher 32 bits of the Destination Address Register (DAR) of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138032c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
DAR_PTR_HIGH |
| Access |
RW/V |
[31:00] RW/V |
DAR_PTR_HIGH
Destination Address Register (higher 32 bits).
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380330 Register(32 bit) HDMA_WATERMARK_EN_OFF_RDCH_1
HDMA Read Channel Linked-list Watermark Enable Register.
This register controls the watermark interrupts generated after processing a watermarked LL element. HDMA updates this field as LL elements are processed.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380330 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
| Name |
- |
LWIE |
RWIE |
| Access |
- |
RW/V |
RW/V |
[01:01] RW/V |
LWIE
Enables Local Interrupts at watermark events (end of linked list element) in an HDMA read channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
[00:00] RW/V |
RWIE
Enables Remote Interrupts at watermark events (end of linked list element) in an HDMA read channel.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380334 Register(32 bit) HDMA_CONTROL1_OFF_RDCH_1
HDMA Read Channel Control Settings 1 Register.
This register controls the operation of the HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380334 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffe00 |
|
|
Undefined |
0xfffffe00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
T_BIT_SRC |
T_BIT |
AT |
RO |
DST_SNOOP |
SRC_SNOOP |
MEM_TYPE |
LLEN |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[08:08] RW |
T_BIT_SRC
Completion to Memory Write T-bit source. The HDMA read channel uses this field to overwrite the T field of the IDE prefix from the core completions by the T_BIT field.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Enable |
0x1 |
Overwrite the T field of the Core completion IDE prefix by the T_BIT field value. |
| Disable |
0x0 |
Forward the T-bit as-is. |
|
[07:07] RW |
T_BIT
T-bit TLP Header Bit. Used in the IDE Prefix for IDE TLPs to indicate that DMA TLP is part of a trusted execution environment. The HDMA read channel uses this TLP header field when generating MRd/IMWr TLP requests.
When T_BIT_SRC field is set to 0x1, the HDMA uses this TLP header field when generating MWr TLP requests.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[06:05] RW |
AT
Address Translation Services TLP Header Bit (AT). The HDMA read channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[04:04] RW |
RO
Relaxed Ordering TLP Header Bit. HDMA read channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[03:03] RW |
DST_SNOOP
Destination No Snoop TLP Header Bit. The HDMA read channel uses this TLP header field when generating MWr/IMWr (DAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[02:02] RW |
SRC_SNOOP
Source No Snoop TLP Header Bit. The HDMA read channel uses this TLP header field when generating MRd (SAR addressing space) TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
[01:01] RW |
MEM_TYPE
Master AXI ACE-Lite Cache Coherency Control. This field sets the HDMA read channel memory type of the address space of the data transfer as follows: For more information, see "ACE-Lite Features and Limitations" section of the Databook. Irrespective of the value of this field, Linked list descriptor requests have this attribute set to 0x1.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| MEM_TYPE |
0x1 |
memory type |
| PERIPHERAL |
0x0 |
peripheral type |
|
[00:00] RW |
LLEN
This field enables the HDMA read channel Linked List mode.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Disable |
0x0 |
Disable |
| Enable |
0x1 |
Enable |
|
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+0x00380338 Register(32 bit) HDMA_FUNC_NUM_OFF_RDCH_1
HDMA Read Channel Function Number Register.
This register controls HDMA read channel to Physical/Virtual function mapping.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380338 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffffe0 |
|
|
Undefined |
0xffffffe0 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
PF |
| Access |
- |
RW |
[04:00] RW |
PF
DMA Channel Physical Function Number.
DMA channel wide physical function of the generated TLP. The controller uses this field to form the requester ID for requests. Function numbering starts at '0'. When you have enabled SR-IOV, refer to VF and VF_EN fields of this register as well. The behavior is undefined if any value outside of the valid range is set to this field.
At the signal interfaces, DMA drives the XADM / RADM signals d_client[0|1]_tlp_func_num / d_radm_trgt1_func_num.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00;
|
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+0x0038033c Register(32 bit) HDMA_QOS_OFF_RDCH_1
HDMA Read Channel QoS Settings Register.
This register controls the HDMA read channel QoS features.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138033c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00030008 |
|
|
Unaffected |
0xfc00ff00 |
|
|
Undefined |
0xfc00ff00 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
| Name |
- |
PF_DEPTH |
- |
WEIGHT |
TC |
| Access |
- |
RW |
- |
RW |
RW |
[25:16] RW |
PF_DEPTH
This field controls the linked list prefetch allocation space for an HDMA read channel. Each read channel stores PF_DEPTH plus '1' linked list elements. For example, if PF_DEPTH =0, the read channel stores one linked list element. This field must be within the range: [ 0 : floor(CX_DMA_RD_LLQ * CC_NUM_DMA_RD_CHAN / number_of_active_channels) - 1 ].
Note: - If this field is set to a value outside the specified range, data corruption or channel crosstalk may happen. - If PF_DEPTH is changed at run time, only channels in the range: [ 0 : number_of_active_channels - 1 ] can be doorbelled. - This field cannot be changed while any read engine channel is in doorbell state. Doing so might yield undefined results.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x003;
| Valid Values |
| Name | Value(s) | Description |
| Max_Field_value |
0x3ff |
Max value |
| Min_Field_value |
0x0 |
Zero value |
|
[07:03] RW |
WEIGHT
Reserved.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x01;
|
[02:00] RW |
TC
Traffic Class TLP Header Field (TC). The HDMA read channel uses this TLP header field when generating MRd/MWr/IMWr TLPs.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
|
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+0x00380380 Register(32 bit) HDMA_STATUS_OFF_RDCH_1
HDMA Read Channel Status Register.
This register specifies the current operational state of a channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380380 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000003 |
|
|
Unaffected |
0xfffffffc |
|
|
Undefined |
0xfffffffc |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
| Name |
- |
STATUS |
| Access |
- |
RO/V |
[01:00] RO/V |
STATUS
HDMA Read Channel Status.
Reset: hex:0x3;
| Valid Values |
| Name | Value(s) | Description |
| ABORTED |
0x2 |
An error condition is detected, and the HDMA has stopped this channel. ERROR field of the HDMA_INT_STATUS_OFF_RDCH_0 register specifies the error. |
| RESERVED |
0x0 |
Reserved |
| RUNNING |
0x1 |
This channel is active and transferring data. |
| STOPPED |
0x3 |
The HDMA has transferred all data for this channel. |
|
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+0x00380384 Register(32 bit) HDMA_INT_STATUS_OFF_RDCH_1
HDMA Read Channel Interrupt Status Register.
This register provides information regarding the HDMA read channel interrupt status.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380384 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RO/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
ERROR |
ABORT |
WATERMARK |
STOP |
| Access |
- |
RO/V |
RO/V |
RO/V |
RO/V |
[06:03] RO/V |
ERROR
HDMA Read Channel Error Interrupt Status. Specifies the error that caused the HDMA to change HDMA_STATUS_OFF_RDCH_i.STATUS to ABORTED state.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| DATA_CPL_TIMEOUT |
0x08 |
CPL timeout while reading data from the source. Only valid for Read Channels. |
| DATA_CPL_UR |
0x09 |
Unsuported request CPL while reading data from the source. |
| DATA_MWR |
0x0c |
Error response received while writing data to the destination. Only valid for Read Channels with AXI bridge (AMBA_INTERFACE >2). |
| LL_CPL_UR |
0x1 |
Unsuported request CPL while reading a linked list element. |
| NONE |
0x0 |
No error to report. This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.ABORT_CLEAR =1 |
| DATA_CPL_CA |
0x0a |
Completer abort CPL while reading data from the source. |
| DATA_CPL_EP |
0x0b |
Poisoned data CPL while reading data from the source. Only valid if CC_DMA_ABORT_ON_POISONED is set. |
| LL_CPL_CA |
0x2 |
Completer abort CPL while reading a linked list element. |
| LL_CPL_EP |
0x3 |
Poisoned data CPL while reading a linked list element. |
|
[02:02] RO/V |
ABORT
HDMA Read Channel Abort Interrupt Status. ABORT and STOP register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.ABORT_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_RDCH_i.LAIE =1 and a local interrupt is generated, this field indicates that an error is detected for this channel. |
|
[01:01] RO/V |
WATERMARK
HDMA Read Channel Watermark Interrupt Status.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.WATERMARK_CLEAR =1 |
| Set |
0x1 |
If HDMA_WATERMARK_EN_OFF_RDCH_i.LWIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for an element with the LWIE bit set. |
|
[00:00] RO/V |
STOP
HDMA Read Channel Stop Interrupt Status. STOP and ABORT register fields are mutually exclusive.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
This field is cleared when HDMA_INT_CLEAR_OFF_RDCH_i.STOP_CLEAR =1 |
| Set |
0x1 |
If HDMA_INT_SETUP_OFF_RDCH_i.LSIE =1 and a local interrupt is generated, this field indicates that HDMA has transferred all the data for this channel. |
|
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+0x00380388 Register(32 bit) HDMA_INT_SETUP_OFF_RDCH_1
HDMA Read Channel Interrupt Setup Register.
This register is used to configure interrupts for a read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380388 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000007 |
|
|
Unaffected |
0xffffff80 |
|
|
Undefined |
0xffffff80 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
| Name |
- |
LAIE |
RAIE |
LSIE |
RSIE |
ABORT_MASK |
WATERMARK_MASK |
STOP_MASK |
| Access |
- |
RW |
RW |
RW |
RW |
RW |
RW |
RW |
[06:06] RW |
LAIE
HDMA Read Channel Local Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in abort conditions. |
|
[05:05] RW |
RAIE
HDMA Read Channel Remote Abort Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in abort conditions. |
|
[04:04] RW |
LSIE
HDMA Read Channel Local Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables local interrupts in stop conditions. |
|
[03:03] RW |
RSIE
HDMA Read Channel Remote Stop Interrupt Enable.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field enables remote interrupts in stop conditions. |
|
[02:02] RW |
ABORT_MASK
HDMA Read Channel Abort Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for abort interrupts. |
|
[01:01] RW |
WATERMARK_MASK
HDMA Read Channel Watermark Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for watermark interrupts. |
|
[00:00] RW |
STOP_MASK
HDMA Read Channel Stop Interrupt Mask.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x1;
| Valid Values |
| Name | Value(s) | Description |
| Clear |
0x0 |
Clear |
| Set |
0x1 |
Setting this field masks the local interrupt pin for stop interrupts. |
|
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+0x0038038c Register(32 bit) HDMA_INT_CLEAR_OFF_RDCH_1
HDMA Read Channel Interrupt Clear Register.
This register indicates interrupt clear status of a read channel. It is a self-clearing register. Reads to this register returns '0'.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138038c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access WS/V
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xfffffff8 |
|
|
Undefined |
0xfffffff8 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
| Name |
- |
ABORT_CLEAR |
WATERMARK_CLEAR |
STOP_CLEAR |
| Access |
- |
WS/V |
WS/V |
WS/V |
[02:02] WS/V |
ABORT_CLEAR
HDMA Abort Channel Abort Interrupt Clear. Setting this field clears the ABORT and ERROR fields.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the ABORT and ERROR fields of the HDMA_INT_STATUS_OFF_RDCH_i register. |
| Clear |
0x0 |
Clear |
|
[01:01] WS/V |
WATERMARK_CLEAR
HDMA Read Channel Watermark Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the WATERMARK field of the HDMA_INT_STATUS_OFF_RDCH_i register. |
| Clear |
0x0 |
Clear |
|
[00:00] WS/V |
STOP_CLEAR
HDMA Read Channel Stop Interrupt Clear.
Reset: hex:0x0;
| Valid Values |
| Name | Value(s) | Description |
| Set |
0x1 |
Setting this field clears the STOP field of the HDMA_INT_STATUS_OFF_RDCH_i register. |
| Clear |
0x0 |
Clear |
|
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+0x00380390 Register(32 bit) HDMA_MSI_STOP_LOW_OFF_RDCH_1
HDMA Read Stop Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380390 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Stop Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380394 Register(32 bit) HDMA_MSI_STOP_HIGH_OFF_RDCH_1
HDMA Read Stop Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Stop Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380394 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_STOP_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_STOP_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Stop Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x00380398 Register(32 bit) HDMA_MSI_WATERMARK_LOW_OFF_RDCH_1
HDMA Read Watermark Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x01380398 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Watermark Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x0038039c Register(32 bit) HDMA_MSI_WATERMARK_HIGH_OFF_RDCH_1
HDMA Read Watermark Remote Interrupt Address High Register.
This register holds the higher 32 bits of the Watermark Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0138039c at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_WATERMARK_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_WATERMARK_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Watermark Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffffffff |
Max Val |
|
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+0x003803a0 Register(32 bit) HDMA_MSI_ABORT_LOW_OFF_RDCH_1
HDMA Read Abort Remote Interrupt Address Low Register.
This register holds the lower 32 bits of the Abort Interrupt MWr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013803a0 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_LOW |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_LOW
The HDMA uses this field to generate bits [31:0] of the address field for the Abort Interrupt MWr TLP. Bits [1:0] must be '00' as this address must be dword aligned.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
| Valid Values |
| Name | Value(s) | Description |
| Max_Val |
0x0ffffffff |
Max Va |
| Min_Val |
0x0 |
Min Val |
|
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+0x003803a4 Register(32 bit) HDMA_MSI_ABORT_HIGH_OFF_RDCH_1
HDMA Read Abort Remote Interrupt Address High.
This register holds the higher 32 bits of the Abort Interrupt mwr TLP address.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013803a4 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
, fully affected, fully defined |
0x00000000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
MSI_ABORT_ADDR_HIGH |
| Access |
RW |
[31:00] RW |
MSI_ABORT_ADDR_HIGH
The HDMA uses this field to generate bits [63:32] of the address field for the Abort Interrupt MWr TLP.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x00000000;
|
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+0x003803a8 Register(32 bit) HDMA_MSI_MSGD_OFF_RDCH_1
HDMA Read Channel Remote Interrupt Data Register.
This register holds the IMWr TLP Data of an HDMA read channel.
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x013803a8 at NOC.pcie__DWC_pcie_dbi__MemSpace (Mem)
Access RW
| Reset Information | |
| Prio |
Type |
Properties |
Value/Mask (hex) |
| 0 |
PowerUp |
|
0x00000000 |
|
|
Unaffected |
0xffff0000 |
|
|
Undefined |
0xffff0000 |
| Bit |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reset |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| Name |
- |
MSI_MESSAGE |
| Access |
- |
RW |
[15:00] RW |
MSI_MESSAGE
The HDMA read channel uses this field to generate the data field for every IMWr TLPs it generates.
Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W
Reset: hex:0x0000;
| Valid Values |
| Name | Value(s) | Description |
| Min_Val |
0x0 |
Min Val |
| Max_Val |
0x0ffff |
Max Val |
|
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