Registers in AddressMap abc_soc_top/dlnk/pcieabc78/DWC_pcie_dbi/DWC_PCIE_USP

PCI_TYPE0_DEVICE_ID

- DEVICE_ID [31:16]
- The Device ID register identifies the particular Function for PCIe Type0 and Type1 configuration header. This identifier is allocated by the vendor.
Databook.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x0dd6;

PCI_TYPE0_VENDOR_ID

Vendor ID.
The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x8086;

DETECTED_PARITY_ERR

Detected Parity Error.

Reset: hex:0x0;

SIGNALED_SYS_ERR

Signaled System Error.

Reset: hex:0x0;

RCVD_MASTER_ABORT

Received Master Abort.

Reset: hex:0x0;

RCVD_TARGET_ABORT

Received Target Abort.

Reset: hex:0x0;

SIGNALED_TARGET_ABORT

Signaled Target Abort.

Reset: hex:0x0;

DEV_SEL_TIMING

DEVSEL Timing.
This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this field to 00b.

Reset: hex:0x0;

MASTER_DPE

Master Data Parity Error.
This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs:
- Function receives a Poisoned Completion
- Function transmits a Poisoned Request
If the Parity Error Response bit is 0b, this bit is never set.

Reset: hex:0x0;

FAST_B2B_CAP

Fast Back to Back Transaction Capable.
This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.

Reset: hex:0x0;

RSVDP_22

Reserved for future use.

Reset: hex:0x0;

FAST_66MHZ_CAP

66MHz Capable.
This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.

Reset: hex:0x0;

CAP_LIST

Capabilities List.
Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.

Reset: hex:0x1;

INT_STATUS

Emulation interrupt pending.
When set, indicates that an INTx emulation interrupt is pending internally in the Function. Setting the Interrupt Disable bit has no effect on the state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires this bit to 0b.

Reset: hex:0x0;

RSVDP_17

Reserved for future use.

Reset: hex:0x0;

PCI_TYPE_RESERV

Reserved.

Reset: hex:0x00;

PCI_TYPE0_INT_EN

Interrupt Disable.
Controls the ability of a Function to generate INTx emulation interrupts.

When set, Functions are prevented from asserting INTx interrupts.

Note:

Any INTx emulation interrupts already asserted by the Function must be de-asserted when this bit is Set. INTx interrupts use virtual wires that must, if asserted, be de-asserted using the appropriate Deassert_INTx message(s) when this bit is set.

Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected.

For functions that generate INTx interrupts, this bit is required. For functions that do not generate INTx interrupts, this bit is optional.

Reset: hex:0x0;

RSVDP_9

Reserved for future use.

Reset: hex:0x0;

PCI_TYPE0_SERREN

SERR# Enable.
When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.

Note: The errors are reported if enabled either through this bit or
through the PCI Express specific bits in the Device Control register.

Reset: hex:0x0;

PCI_TYPE_IDSEL_STEPPING

IDSEL Stepping/Wait Cycle Control.
This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.

Reset: hex:0x0;

PCI_TYPE0_PARITY_ERR_EN

Parity Error Response.
This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register.

Reset: hex:0x0;

PCI_TYPE_VGA_PALETTE_SNOOP

VGA Palette Snoop.
This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge architecture specification. Its functionality does not apply to PCI Express, the controller hardwires this bit to 0b.

Reset: hex:0x0;

PCI_TYPE_MWI_ENABLE

Memory Write and Invalidate.
This bit was originally described in the PCI Local Bus Specification and the
PCI-to-PCI Bridge architecture specification. Its functionality does not apply
to PCI Express, the controller hardwires this bit to 0b.

Reset: hex:0x0;

PCI_TYPE0_SPECIAL_CYCLE_OPERATION

Special Cycle Enable.
This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.

Reset: hex:0x0;

PCI_TYPE0_BUS_MASTER_EN

Bus Master Enable.
Controls the ability of a Function to issue Memory and I/O Read/Write requests.
- When this bit is set, the Function is allowed to issue Memory or I/O Requests.
- When this bit is clear, the Function is not allowed to issue any Memory or I/O Requests.
Requests other than Memory or I/O Requests are not controlled by this bit.

Note: MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.


Note: The access attributes of this field are as follows:
- Wire: R/W
- Dbi: R/W

Reset: hex:0x0;

PCI_TYPE0_MEM_SPACE_EN

Memory Space Enable.
Controls a Function's response to Memory Space accesses.
- When this bit is set, the Function is enabled to decode the address and further process Memory Space accesses.
- When this bit is clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.
For a Function does not support Memory Space accesses, the controller hardwires this bit to 0b.


Note: The access attributes of this field are as follows:
- Wire: !has_mem_bar ? RO : RW
- Dbi: !has_mem_bar ? RO : RW

Reset: hex:0x0;

PCI_TYPE0_IO_EN

IO Space Enable.
Controls a Function's response to I/O Space accesses.
- When this bit is set, the Function is enabled to decode the address and further process I/O Space accesses.
- When this bit is clear, all received I/O accesses are caused to be handled as Unsupported Requests.
For a Function that does not support I/O Space accesses, the controller hardwires this bit to 0b.


Note: The access attributes of this field are as follows:
- Wire: !has_io_bar ? RO : RW
- Dbi: !has_io_bar ? RO : RW

Reset: hex:0x0;

BASE_CLASS_CODE

Base Class Code.
A code that broadly classifies the type of operation the Function performs.
Encodings for base class, are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x02;

SUBCLASS_CODE

Sub-Class Code.
Specifies a base class sub-class, which identifies more specifically the operation of the Function.
Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x80;

PROGRAM_INTERFACE

Programming Interface.
This field identifies a specific register-level programming interface (if any) so that device independent software can interact with the Function.
Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x00;

REVISION_ID

Revision ID.
The value in this register specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x01;

BIST

BIST.
This register is used for control and status of BIST. For Functions that do not support BIST the controller hardwires the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link.
Bit descriptions:
- [31]: BIST Capable.
When Set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST.
- [30]: Start BIST.
If BIST Capable is Set, Set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been Set. Writing this bit to 0b has no effect. This bit must be hardwired to 0b if BIST Capable is Clear.
- [29:28]: Reserved.
- [27:24]: Completion Code.
This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is Set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.

Reset: hex:0x00;

MULTI_FUNC

Multi-Function Device.
Except where stated otherwise, it is recommended that this bit be set if there are multiple Functions, and clear if there is only one Function.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x0;

HEADER_TYPE

Header Layout.
This field identifies the layout of the second part of the predefined header.
The controller uses 000 0000b encoding.

Reset: hex:0x00;

LATENCY_MASTER_TIMER

Latency Timer.
The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.

Reset: hex:0x00;

CACHE_LINE_SIZE

Cache Line Size.
The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express device
behavior.

Reset: hex:0x00;

BAR0_START

- BAR0_START. BAR0 Base Address.
- Memory Space: Base Address.
- IO Space: bits[31:2] are used to map the function into IO space/Base Address.


Note: The access attributes of this field are as follows:
- Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky)
- Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky)
Note: This register field is sticky.

Reset: hex:0x0000000;

BAR0_PREFETCH

- BAR0 Prefetchable.

Memory Space: Set to one if data is prefetchable.

A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.

IO Space: Not applicable.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR0_TYPE

- BAR0 Type.
- Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply.
- IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x2;

BAR0_MEM_IO

- BAR0 Memory Space Indicator.
- This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.
- Base Address registers that map to I/O Space must return a 1b.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR1_START

- BAR1 Base Address.
- Memory Space: Base Address.
- IO Space: bits[31:2] are used to map the function into IO space/Base Address.


Note: The access attributes of this field are as follows:
- Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky)
- Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky)
Note: This register field is sticky.

Reset: hex:0x0000000;

BAR1_PREFETCH

- BAR1 Prefetchable.

Memory Space: Set to one if data is prefetchable.

A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.

IO Space: Not applicable.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR1_TYPE

- BAR1 Type.
- Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply.
- IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR1_MEM_IO

- BAR1 Memory Space Indicator.
- This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.
- Base Address registers that map to I/O Space must return a 1b.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR2_START

BAR2 Base Address.
- Memory Space: Base Address.
- IO Space: bits[31:2] are used to map the function into IO space/Base.
Address.


Note: The access attributes of this field are as follows:
- Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky)
- Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky)
Note: This register field is sticky.

Reset: hex:0x0000000;

BAR2_PREFETCH

BAR2 Prefetchable.
- Memory Space: Set to one if data is prefetchable.
A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.
- IO Space: Not applicable


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR2_TYPE

BAR2 Type.
- Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply.
- IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x2;

BAR2_MEM_IO

BAR2 Memory Space Indicator.
This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.
Base Address registers that map to I/O Space must return a 1b.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR3_START

BAR3 Base Address.
- Memory Space: Base Address.
- IO Space: bits[31:2] are used to map the function into IO space/Base.
Address.


Note: The access attributes of this field are as follows:
- Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky)
- Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky)
Note: This register field is sticky.

Reset: hex:0x0000000;

BAR3_PREFETCH

BAR3 Prefetchable.
- Memory Space: Set to one if data is prefetchable.
A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.
- IO Space: Not applicable


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR3_TYPE

BAR3 Type.
- Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply.
- IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR3_MEM_IO

BAR3 Memory Space Indicator.
This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.
Base Address registers that map to I/O Space must return a 1b.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR4_START

BAR4 Base Address.
- Memory Space: Base Address.
- IO Space: bits[31:2] are used to map the function into IO space/Base.
Address.


Note: The access attributes of this field are as follows:
- Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky)
- Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky)
Note: This register field is sticky.

Reset: hex:0x0000000;

BAR4_PREFETCH

BAR4 Prefetchable.
- Memory Space: Set to one if data is prefetchable.
A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.
- IO Space: Not applicable


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR4_TYPE

BAR4 Type.
- Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply.
- IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR4_MEM_IO

BAR4 Memory Space Indicator.
This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.
Base Address registers that map to I/O Space must return a 1b.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR5_START

BAR5 Base Address.
- Memory Space: Base Address.
- IO Space: bits[31:2] are used to map the function into IO space/Base.
Address.


Note: The access attributes of this field are as follows:
- Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky)
- Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky)
Note: This register field is sticky.

Reset: hex:0x0000000;

BAR5_PREFETCH

BAR5 Prefetchable.
- Memory Space: Set to one if data is prefetchable.
A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise.
- IO Space: Not applicable


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR5_TYPE

BAR5 Type.
- Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The encodings defined in Values: apply.
- IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space. The encodings defined in Values: do not apply.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

BAR5_MEM_IO

BAR5 Memory Space Indicator.
This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.
Base Address registers that map to I/O Space must return a 1b.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky)
Note: This register field is sticky.

Reset: hex:0x0;

CARDBUS_CIS_POINTER

CardBus CIS Pointer.
Its functionality does not apply to PCI Express. It must be hardwired to 0000 0000h.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x00000000;

SUBSYS_DEV_ID

Subsystem ID.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x0dd6;

SUBSYS_VENDOR_ID

Subsystem Vendor ID.
Subsystem Vendor IDs can be obtained from the PCI SIG and are used to identify the vendor of the add-in card or subsystem. Values for the Subsystem ID are vendor-specific.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x8086;

EXP_ROM_BASE_ADDRESS

Expansion ROM Base Address.
Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires.


Note: The access attributes of this field are as follows:
- Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R
- Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R

Reset: hex:0x000000;

RSVDP_8

Reserved for future use.

Reset: hex:0x0;

ROM_BAR_VALIDATION_DETAILS

Expansion ROM Validation Details.
The field contains optional, implementation-specific details associated with Expansion ROM Validation.
- If validation is in progress (Expansion ROM Validation Status is 001b), non-zero values of this field represent implementation-specific indications of the phase of the validation progress (for example, 50% complete). The value 0000b indicates that no validation progress information is provided.
- If validation is completed (Expansion ROM Validation Status 010b to 111b inclusive), non-zero values in this field represent additional implementation-specific information. The value 0000b indicates that no information is provided.
- When validation is supported and this field is not implemented, this field must be hardwired to 0000b.


Note: The access attributes of this field are as follows:
- Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R
- Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1 && DBI_RO_WR_EN == 1 ) then R/W else R
Note: This register field is sticky.

Reset: hex:0x0;

ROM_BAR_VALIDATION_STATUS

Expansion ROM Validation Status.
When this field is non-zero, it indicates the status of hardware validation of the Expansion ROM contents.
- If the Function does not support validation, this field must be hardwired to 000b.
- It is optional whether an implementation is capable of returning Validation Status values 011b, 101b, 110b, or 111b.


Note: The access attributes of this field are as follows:
- Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R
- Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1 && DBI_RO_WR_EN == 1) then R/W else R
Note: This register field is sticky.

Reset: hex:0x0;

ROM_BAR_ENABLE

Expansion ROM Enable.
This bit controls whether or not the Function accepts accesses to its expansion ROM.
The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.


Note: The access attributes of this field are as follows:
- Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R
- Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R

Reset: hex:0x0;

RSVDP_8

Reserved for future use.

Reset: hex:0x000000;

CAP_POINTER

Capabilities Pointer. This register points to a valid capability structure. Either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are reserved, the controller sets it to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.


Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
Note: This register field is sticky.

Reset: hex:0x40;

RSVDP_16

Reserved for future use.

Reset: hex:0x0000;

INT_PIN

Interrupt Pin.
The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses. All encodings other than the defined encodings are reserved.
PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.

Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth.
For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.

Note: The access attributes of this field are as follows:
- Wire: R (sticky)
- Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
Note: This register field is sticky.

Reset: hex:0x01;

INT_LINE

Interrupt Line.
The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin.
Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.

Reset: hex:0xff;